EMC-3D Consortium Targets Cost-Effective TSV Interconnects
Equipment providers, materials companies and packaging researchers have joined together to form an international consortium that addresses complex integration of through-silicon via (TSV) 3-D interconnects.
Bioh Kim, Semitool, Kalispell, Mont. -- Semiconductor International, 2/1/2007
The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. General advantages of 3-D packaging include the miniaturization of size and weight, the integration of heterogeneous technologies in a single package, the replacement of long 2-D interconnects with short vertical interconnects, and the reduction of parasitics and power consumption. Therefore, 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies.
There are various kinds of 3-D packages based on stacking methods, which include on-chip 3-D integration based on layer-by-layer build-up of functional layers within a chip; 3-D stacking with die-to-die stacking or package-to-package stacking (package-on-package [POP] or package-in-package [PIP]); and 3-D ICs (3-D integration of ICs), which have die-to-die interconnection with through-silicon vias (TSVs). Among all kinds of 3-D packaging techniques, TSV electrodes can provide the shortest and most plentiful Z-axis connections.
TSV technology is known to have various potential benefits, including:- Connection lengths can be as short as the thickness of a chip, which has the potential to significantly reduce the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally.
- High-density, high-aspect-ratio connections are possible, which allows for the integration of complex, multi-chip systems entirely within the silicon with a physical packing density many times better than today's advanced multi-chip modules.
- RC delays of long, in-plane interconnects are avoided by bringing out-of-plane logic blocks much closer electrically.
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| Source: Semitool |
- Via formation
- Insulator, barrier and seed deposition
- Copper filling (plating), removal and redistribution lines (RDL) plating
- Wafer thinning
- Wafer/chip alignment, bonding and dicing
Most of those technologies are quite new to the packaging industry, and also require huge investments with high risk. That's why 3-D ICs are still at the R&D stage, even in the largest IC companies today.
Key technical issues and challenges for TSV interconnects that are not fully resolved include:- Drilling the vias — laser vs. deep reactive ion etch (DRIE)
- Filling the vias — materials (polysilicon, copper, tungsten, conductive polymer, etc.) and techniques (electroplating, chemical vapor deposition [CVD], polymer coating, etc.)
- Process flow — via-first or via-last
- Stacking — wafer-to-wafer, chip-to-wafer or chip-to-chip
- Bonding — direct Cu-Cu, adhesive, direct fusion, solder, hybrid, etc.,
- Thin wafer handling — with or without carrier
To minimize both the risk of failure and trial and error, cooperation with industrial leaders in equipment, materials and research is mandatory for most of companies that are developing or planning to develop TSV technology.
To help the packaging industry resolve the technical issues and develop a cost-effective technology, a new industrial consortium was organized in September 2006. The EMC-3D , a semiconductor 3-D equipment and materials consortium, is addressing the technical and economic issues of creating 3-D interconnects using TSV technology for chip stacking and advanced MEMS/sensors packaging. Several major equipment manufacturers have joined with material companies to work with key research groups to address the issues of cost-effective manufacturing and integration.
Equipment companies initiating the consortium as founding members are:- Alcatel Micro Machining Systems (Annecy, France) for via etch
- XSiL (Dublin, Ireland) for laser drill and dicing
- Semitool (Kalispell, Mont.) for wet processes (via plating, RDL plating and wafer thinning)
- EV Group (Schärding, Austria) for wafer/die alignment and stacking
- Fraunhofer IZM (Institute for Reliability and Mikrointegration, Chemnitz, Germany)
- LETI (Laboratoire d'électronique et de technologie de I'information, Grenoble, France)
- SAIT (Samsung Advanced Institute of Technology, Seoul, Korea)
- KAIST (Korea Advanced Institute of Science and Technology, Daejeon, Korea)
- TAMU (Texas A&M University, College Station, Texas)
- Rohm and Haas Electronic Materials PFT (Packaging and Finishing Technologies, Freeport, N.Y.)
- Enthone Inc. (West Haven, Conn.)
- AZ Electronic Materials (Somerville, N.J.)
- Honeywell (Spokane, Wash.), with wafer thinning service support from Isonics Corp. (Vancouver, Wash.)
Through collaboration with research partners, the consortium will develop processes for creating micro vias between 5 and 30 µm on thinned 50 µm 200 and 300 mm wafers using both via-first and via-last techniques.
Major processes being integrated into the EMC-3D program are:
- Via DRIE etch and laser drill
- Insulator/barrier/seed deposition
- Micro via patterning with RDL capabilities
- High-aspect-ratio copper plating
- Carrier bonding/debonding
- Sequential wafer thinning
- Backside insulator/barrier/seed deposition
- Backside lithography
- Backside contact metal plating
- Chip-to-wafer placement and attach
- Laser dicing
In addition, wafer-to-wafer attach, dicing and debonding will be demonstrated. The cost of ownership goal for the integrated 3-D process is $200/wafer.
| Author Information |
| Bioh Kim is the business development manager of 3-D packaging at Semitool . He received his B.S. and M.S. degrees in metallurgical engineering from Seoul National University in Seoul, Korea. Within Semitool, he had been working as a senior process engineer for electrochemical deposition (ECD) process development related to packaging applications for 6 years, and joined the ECD marketing group in September 2005. Phone: 406-752-2107 Email: bkim@emc3d.org |
