Deep Silicon Etching: An Enabler for 3-D Integration

Through-silicon via etching is used to manufacture MEMs, power devices and, lately, 3-D structures.

Dave Thomas, Aviza Technology Inc., Scotts Valley, Calif. -- Semiconductor International, 2/1/2007

In 2004, Sematech observed that process and material changes to interconnects would not enable the required performance enhancements in next-generation ICs, and predicted that the needed boost may come from heterogeneous integration of dissimilar devices.¹ Device manufacturers and packaging houses are looking to wafer-level packaging (WLP) techniques to address the demands of future product miniaturization and increased functionality. Products that will ultimately benefit from this type of scaling include digital cameras, cell phones and PDAs.

3-D integration is one type of WLP method whereby two or more planar devices are stacked and connected. Multiple approaches in WLP include wire and flip-chip bonding, but a more sophisticated and performance-enhancing method involves the use of through-wafer vias. In 2007, the International Technology Roadmap for Semiconductors (ITRS) will incorporate and track the design nodes and architectures for 3-D interconnect for the first time.

Through-wafer via technology

Deep silicon etching, based on the Bosch gas switched process, was originally conceived and is still being used for MEMS device fabrication. However, it is also an enabling technology for new ranges of power devices (deeper trenches for higher voltage and current handling) and etching through-silicon vias (Fig. 1 ). The process involves fast switching between silicon etching and polymer deposition for silicon sidewall protection, with SF₆ and C₄F₈ being the principal process gases for the etch and deposition cycles, respectively. Benefits of the switched approach (typical step times being 1-3 sec) include high etch rates and mask selectivities that cannot be achieved by single-step silicon etching. A disadvantage is “scalloping” of the sidewall, an artifact of the etch and deposition cycles. However, with proper process optimization, scalloping can be minimized (Fig. 2 ).

Ownership

1. Deep silicon etching uses SF6 and C4F8 process gases in fast, alternating deposition and etch cycles.

The growing importance of 3-D packaging has prompted Sematech to develop an industry-wide roadmap to guide 3-D packaging efforts, while IMEC (Leuven, Belgium) is also putting together a consortium with the same end goal. This attention and work will help consolidate the industry effort and promote market acceptance. A range of approaches currently exists, favored by different groups in the IC food chain. Front-end-of-line (FEOL) approaches involve designing in the vias from the onset so that fabrication takes place at the IDM or foundry. The packaging house thins the wafers to reveal the vias and make the IC-to-IC bond. Alternatively, back-end-of-line (BEOL) approaches exist whereby the chip designer leaves exclusion zones for the packaging house to add in the vias. This adds value to the packaging activity, but requires skills currently absent from their conventional activities.

Conclusions

Deep silicon etching is an enabling technology for 3-D packaging. Successful integration of through-silicon vias will require close cooperation between etch, oxide deposition and metal seed/fill providers. Cost models for these new technologies are still being calculated, and the logistics of how to “fit” the technology into the existing IC food chain will continue to be explored and discussed.

2. These etched 40 µm circular trenches (top left), are lined with SiO2 and Ti/Cu seed (top right). Shown below are the etch via sidewall and bottom corner.