Notable Changes to the 2006 ITRS

The 2006 update to the International Technology Roadmap for Semiconductor (ITRS), released in December, remains largely unchanged from the 2005 ITRS, which represented a major revision. One exception is that double patterning was added as an additional potential solution for lithography at 45 nm (see “Achieving 45 nm HP Without a Wavelength Change ”).

Another major exception is found in the front-end process and process integration areas, where the deployment of high-k and metal gate technology is delayed by two years, until 2010, at least for high-performance and low operating power (LOP) devices. In 2005, high-k and metal gates were forecasted to come online in 2008.

Similarly, the projected implementation of fully depleted ultrathin body silicon on insulator (SOI) MOSFETs for high-performance logic is delayed from 2008 (as forecasted in the 2005 ITRS) until 2010.

The reason for these delays, noted in the ITRS, is that it now seems unlikely that the IC industry will find it feasible to deploy these innovations as early as 2008. However, for low standby power (LSTP) logic, the projected implementation of high-k gate dielectric and metal gate electrode is in 2008, as forecasted in the 2005 ITRS. For LSTP, the relatively thick dielectric equivalent oxide thickness (EOT) of 1.6 nm and potential use of fully silicided gate electrodes make the 2008 deployment more feasible than for LOP and high-performance logic.

The consequences of the delay in deploying high-k gate dielectric and metal gate electrode were analyzed for the affected years, 2008 and 2009. The scaling of the EOT of the gate dielectric is slowed in 2008 and 2009, compared with that in the 2005 PIDS tables, in order to keep the gate leakage current within tolerable limits. Other consequences for those two years include increases in the source/drain leakage current and some slowing in the scaling of the transistor intrinsic delay, τ.

τ=CV_dd/I_dsat

where C is the load capacitance, V_dd is the power supply voltage, and I_dsat is the transistor saturation drive current. Since C is inversely proportional to the EOT, both C and I_dsat are reduced for 2008 and 2009.

The 2006 ITRS was also updated with regard to DRAM capacitors, including the use high-k dielectrics for stacked capacitors and, for trench capacitors, the use of nitrided oxide dielectric was been extended through the 70 nm generation, with high-k materials being introduced at 65 nm. In addition, for the DRAM trench capacitor, new integration schemes to be introduced at 40 nm will reduce the thermal budget for the cell capacitor. Thus, a more aggressive scaling of the capacitance EOT will be possible. As a consequence, the trench aspect ratio can be kept at <100 down to the 28 nm generation.

In recognition of the increasing importance of the dynamic power dissipated in the interconnect structure, a new power metric has been added to the MPU and ASIC technology requirements tables. The power metric is the power (measured in Watts) dissipated per gigahertz of frequency and centimeters squared of metal layer. Although the power metric is seen to plateau for the long-term years because of aggressive introduction of low-k dielectrics, the power dissipated in the interconnect structure will still increase dramatically because of higher frequencies and increases in the number of metal layers. This metric is a measure of the dynamic power associated with the interconnect structure, and the actual power dissipation of a specific device will be a function of architecture and implementation of power-saving design features.

In addition to the power metric, the capacitance per unit length for Metal 1, intermediate, and minimum global wiring layers has also been added to the tables for 2006. The copper resistivity of these layers had been added in prior years and, with the addition of capacitance, the RC values can easily be calculated. The metric for interlevel metal insulator — bulk dielectric constant (k) — has also been changed for 2006. In prior roadmaps, this metric had been listed as the minimum expected for each year. This metric has been replaced with a range of values depicting both the most aggressive bulk dielectric constant expected as well as a more realistic case. This range of bulk k values was then used to calculate the metric, which lists the range of k_eff values for each of the roadmap years. One grand challenge reflects the rapid introductions of new materials and processes necessary to meet conductivity requirements and reduce the dielectric permittivity. Another grand challenge is managing the variability associated with line-edge roughness (LER), trench and via depth and profile, etch bias, and thinning caused by cleaning and chemical mechanical planarization (CMP), as well as size effects. Traditional interconnect scaling will no longer satisfy performance requirements. Solutions beyond copper and low-k will require material innovation, combined with accelerated design, packaging and unconventional interconnect approaches.

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