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Nanotech Looks Beyond Fundamental Limits

Alexander E. Braun, Senior Editor -- Semiconductor International, 2/1/2007

Conventional metrology techniques continue to be applied to increasingly smaller and complex structures, and many current techniques are rushing toward a near future when they will be blind and incapable to meet quality control and failure analysis requirements. Engineers can no longer take for granted that the necessary metrology will be available for new device architecture requirements.

Robert Geer, associate professor of nanoscience at the College of Nanoscale Science and Engineering of the University of Albany (New York), heads a program, based on nanomechanics, focused on fundamental metrology R&D. A critical area is mask defects — specifically, extreme ultraviolet (EUV) lithography masks. A complication is that EUV optics are reflective. Instead of a reticle through which light shines, a multilayer reflective mask is used. Reflective mask defects are amplified when the coating is applied; thus, mask blanks and the mask itself must be extraordinarily defect-free — tolerance for >50 nm particles is zero.

A hurdle is how to clean off these particles, and whether available technology can do it. Albany is working with Sematech (Austin, Texas) to measure defect particle nanomechanics, model how particles adhere to the mask, and create cleaning solutions and flow conditions. A custom instrument has been built, which combines an atomic force microscope tip integrated in a microfluidic flow system that is placed directly on an EUV mask blank, and can detect a particle 20 nm across and measure its adhesive strength to an EUV mask blank. This means understanding how adhesive forces operate between a mask and a strangely shaped 20 nm particle with different chemical properties.

A parallel research effort is observing mechanics in different parts of a structure. Most logic chip manufacturers depend on strained silicon for performance enhancement. They either squeeze or stretch the silicon in the channel region, enabling electrons to travel faster. Silicon on insulator (SOI) is a boon to logic because it decouples the active area from the substrate's capacitance. However, when SOI and strained silicon are combined, some standard e-beam diffraction approaches for measuring strain and the silicon layer become unsatisfactory. The layer is so small that electron diffraction peaks broaden out, making it difficult to get accurate data on the spacing between the silicon atoms and, therefore, the strain level.

Albany is working with AMD (Sunnyvale, Calif.) and the Semiconductor Research Corp. (Durham, N.C.) to develop an approach using plasmonics, which works like a nano-flashlight. Light shone on a nanoscale silver-tipped particle generates surface plasmons, which create an evanescent wave — a powerful light source that extends for a few nanometers. By placing the nanoprobe close to the strained silicon, Raman scattering is excited from the silicon, making it possible to observe just the channel region (Figure ). The Raman photon's wavelength reveals the strain level. The technique is being developed to provide 10 nm scale resolution.

Combined 3-D nanoscale topography and Raman spectral image of a strained SOI ‘island’ illustrating edge-relaxation effects in an octagonal-patterned SOI test structure. The relative brightness across the 3-D island image denotes the strained silicon Raman intensity. A 2-D color map of the strained silicon Raman intensity is shown in the inset. (Source: University of Albany)

As some traditional techniques falter, wafer slicing becomes necessary. The best approach uses a TEM, making it possible to observe small volumes of atoms. However, when something is sliced thin enough for TEM applications, its mechanical boundaries are altered — the device is unclamped, and it becomes impossible to determine whether the measured strained silicon is like the one in the transistor. A non-destructive or less destructive method is necessary.

Albany is also using optical techniques to observe strain concentration areas that might crack during processing. They are developing a predictive technique because those used to determine elemental composition or film thickness do not necessarily provide a strength-level 3-D picture. Thus, it is difficult to determine when the device is subjected to thermal cycles, whether delamination or cracking might result. A metrology technique revealing whether the line is held on strain control would be useful, and the researchers are working with a nanoprobe to develope a non-destructive measurement technique that covers a larger area. Presently, resolution is <100 nm, and they expect to take it down to ~10 nm. These techniques should be available for the 45 or 32 nm nodes.

Metrology research must get the same priority that areas such as lithography receive. When the fundamental science of the material being worked with and the approach being used are understood, there is tremendous potential for nanoscale characterization and metrology to respond to these needs. We must look beyond those conventional approaches that have served us so well.

Find more information on inspection, measurement and test.

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