IBM, Toshiba, Albany Talk Business Strategy at ITPC

At the recent International Trade Partners Conference (ITPC), held Nov. 5-8 in Maui, several leading device manufacturers and equipment suppliers discussed the importance of collaboration and the role it should play in alliances, funding for R&D, and corporate strategy. Three talks in particular, one from the CEO of Toshiba Semiconductor (Tokyo), the vice president of R&D at IBM Systems and Technology Group (Hopewell Junction, N.Y.), and the president of Albany NanoTech (Albany, N.Y.), gave insight into the state of collaboration and funding.

President and CEO of Toshiba Semiconductor, Masashi Muromachi, stated that Fujitsu (Tokyo), NEC (Tokyo), Renesas (Tokyo) and Toshiba have agreed to define a standard process technology that can be applied to the manufacture of ULSI devices at 45 nm and beyond. They aim to have standard specifications by early 2007, and the standardization will allow access to IP and libraries of the other companies. Muromachi then revealed plans more specific to Toshiba: a desire to be the No. 3 semiconductor manufacturer, and to keep a portfolio of memory, system LSI and discrete devices, with special emphasis on the digital consumer, mobile and automotive markets. They have five core product areas: NAND flash, multi-chip memory products, broadband system LSI, power devices, and image sensors. Its capital spending in 2006 was 350 billion yen, and the expected level over three years (through 2008) is estimated at 1.02 trillion yen. Toshiba's projection for unit volume (bit growth) in NAND flash (Figure) shows a CAGR of 150% from 2005 to 2008. Much of this market expansion is because of the incorporation of video in various products, including digital consumer, audio and handheld products.

Much of the incredible growth in the flash market is fueled by demand for video. The expected CAGR from 2005 to 2008 is 150%. (Source: Toshiba)

In process technology, Toshiba expects to start mass production of 65 nm this quarter. They will complete the development of 45 nm technology with development partners Sony (Tokyo) and NEC Electronics (Kanagawa, Japan), then move on to 32 nm with partners IBM and Sony. The Cell processor engine is expected to be used in three main areas: AV equipment for image recognition and media processing, industrial applications for image data processing and documentation, and medical systems for image data processing and high-bandwidth processing. The Cell contains 234 million transistors, and is capable of performing up to 256 billion floating point operations per second.

Lisa Su, vice president of semiconductor R&D at IBM Systems and Technology Group, discussed innovation vs. pure scaling and the success of collaborative ventures. She said that there was a common GDS process platform between IBM's East Fishkill facility, Chartered Semiconductor Manufacturing's Woodlands campus in Singapore and Samsung 's S1 line in Seoul, Korea. In one example of end-use collaboration, she talked about how IBM and Chartered worked directly with Microsoft to move the Xbox and PS3 microprocessor into volume production in only 24 months.

Su talked about the technology roadmap for 45 and 32 nm, which will include silicon on insulator (SOI), strained silicon, high-k dielectrics, metal gates, low-k dielectrics and copper. At 22 nm, this will also include ultrathin-body SOI, air gap intermetal dielectric and finFETs. Ultralow-k dielectrics will extend from current levels of 2.4 to 2.2 and 2.0 (air gap). Much emphasis in the memory area is on stacking or memory alternatives for higher density at lower cost and power consumption. She showed an SOI-embedded DRAM device cross-section, citing a 3-5× density advantage over 6T SRAMs.

Alain Kaloyeros of Albany NanoTech presented details of the funding behind cooperative ventures at Albany. He claimed the only full-flow 300 mm wafer fab operating in academia. Albany's long-term innovation and funding pipeline includes ~$100M in the National Focus Center Consortium, $50M over 10 years in the Center for Advanced Technology in Nanoelectronics beginning in September 2004, $12.5M over five years in the Center for Advanced Interconnect Science and Technology beginning in January of 2005, and $435M over five years in the Institute for Nanoelectronics Discovery & Exploration in January 2006. Albany currently has three separate cleanroom facilities, and is in the process of building a fourth 15,000 ft² cleanroom. In all, the facilities will cost ~$340M, and are comprised of 152,000 ft² of cleanroom, 85,000 ft² of which will be 300 mm by mid-2008. The AMD, IBM, Qimonda, Micron R&D Center involves an investment of $500M over five years, which began in July 2005.