ISMI Updates Goals, Challenges of 450 mm Wafers

Members of the International Sematech Manufacturing Initiative (ISMI) worked throughout 2006 to delve into the planning and evaluation stages in preparation for an industry transition to 450 mm wafers. After the transition to 300 mm wafers, tool and material suppliers are not so keen to make the next wafer size transition, particularly without proper R&D funding. As Denis Fandel, ISMI project manager, put it, “450 has certainly been somewhat of a lightning rod in the industry from creating a number of different emotions.”

But ISMI, operating on the basis that the 450 mm wafer size is a known eventuality, has set out to systematically analyze and evaluate the best way to make that transition. In the first quarter of 2006, ISMI developed four focus teams — factory architecture, factory simulation, starting materials and economic analysis — to better orchestrate the evaluation. The teams gave updates on their progress at the ISMI Symposium on Manufacturing Effectiveness in October.

There are several issues related to the pursuit of 450 mm wafers, including the financial analysis, the timing of the insertion into production, and the technical feasibility. Return on investment is a major concern, Fandel noted, as well as a source of R&D funding to move the project forward.

According to Fandel, the ISMI approach is to understand the economic impact on the industry, build an industry consensus, and build from lessons learned in the 300 mm transition. The focus in 2006 was really to understand the productivity and economic impact of a 450 mm transition, he noted.

Fandel said the key lessons learned from the 300 mm transition are that industry coordination is crucial, including early engagement of equipment and materials manufacturers; the transition needs to support multiple leading-edge business models; ISMI needs to assess business and economic models; and they need to continuously evaluate and adjust the impact of technology on timing, and market and industry dynamics. “The philosophy here is to really look at 300 mm and see if there are ways to do things differently,” added Tom Abell, an Intel assignee serving as ISMI's 450 mm program manager.

The slowing pace of technology, design shrinks, design layout innovations, etc., are causing a slowdown in productivity. “The gap between cost and productivity going forward looks to be about $150B,” Abell said. “Historically, a wafer size transition has been the way to offset those costs.” Wafer size transitions have tended to come every 10-11 years. With 200 mm coming in around 1990, and 300 mm around 2001, 450 mm should come some time in the 2012 timeframe, he said.

300 Prime is geared toward improving 300 mm productivity while bridging to 450 mm production. “300 Prime is a way of staging that transition, and lowering the risk of that transition,” Abell said. 300 Prime should provide productivity improvements that are scalable to 450 mm.

“There's clearly a need for higher productivity and process controllability — not just from the process equipment, but from the automation, etc.,” Abell said. “As long as we can maintain the productivity benefits that have been historically gained with wafer size transition, 2012 is a good timing with the ITRS .”

Mike Goldstein of Intel holds a 450 mm wafer. The significant wafer size increase would bring with it several challenges along with productivity advantages.

The focus teams gave presentations at the ISMI Symposium. Presenting on 450 mm starting materials, Mike Goldstein of Intel noted challenges in several areas, including the silicon supply chain, material handling, characterization equipment, and wafer specification standardization. The cost of the Czochralski (CZ) puller is the biggest challenge, and would create the largest cost issue. Compared with 300 mm crystals, the pull rate will be slower, the time needed to grow the same length crystal will be longer, crystal yield will be lower, and the silicon charge will be much bigger. Meanwhile, the equipment will have to be much bigger.

Wafer thickness also presents challenges, with larger-diameter wafers requiring increased thickness to preserve their integrity during processing and handling (suggested thickness is 825 µm). The higher diameter-to-thickness aspect ratio for 450 mm wafers increases the risk of slip and breakage during thermal processing because of stress from temperature gradients and gravity; and the degradation of bow and warp during processing may cause problems at various processes such as lithography, flash anneal, etc.

Application-specific wafers such as silicon on insulator (SOI), epitaxial or SiGe wafers will inevitably generate additional challenges, Goldstein added.

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