Dummy Fill Simplified

Dummy insertion — or “dummy fill” — is typically used to compensate for the variations in post-CMP surface topography that result from differences in layout patterns across the chip. Typically, foundries have inserted these non-functional patterns into the design layout using the physical verification tool, which finds unoccupied areas and inserts the prescribed dummy patterns into those areas, making sure to satisfy the CMP design rules. It is done in multiple passes to accommodate various dummy sizes, shapes and locations.

A new, intelligent fill synthesis tool was designed to simplify the dummy fill process. Blaze IF, the second product offering from Blaze DFM (Sunnyvale, Calif.), optimizes dummy insertion without harming chip performance or power. “The existing approach worked fine before we had such complex rules,” said Dave Reed, co-founder of Blaze DFM. “So we built a tool that optimally meets the foundry CMP rules while maintaining power and performance specifications.”

Prior to such a tool, engineers performed fill synthesis using custom scripts written for design rule verification tools. However, the advanced complexity of CMP design rules has caused fill insertion scripts to become overly complex to the point where it is impractical to maintain this approach. “Fill has typically been done by the foundry after the design is closed. But what has happened is the fill would disrupt the timing or power specs of the chip and the customer would get results back and the performance would be off,” Reed said.

For 65 nm processes, dummy fill is often performed on all metallization layers, as well as poly and shallow trench isolation. “You can and should optimize the fill on all layers simultaneously, which would be very difficult to do with a homemade script,” Reed said.

The fill insertion tool is just one component in the company's overall vision for what they term “electrical DFM” — optimizing the design and manufacturing interaction for the best possible electrical results on the chip. The optimization engine consists of all the parameters the designer wants to optimize (leakage power, dynamic power, power variation, timing, etc.), and the tools that can be used to affect these parameters (fill insertion, gate CD biasing, etc.). The analysis engines check that the decisions made by the optimization engines have the desired effect on the operation of the chip in terms of timing behavior, power consumption and the like.

The Blaze IF tool uses timing and power analysis engines to maintain power and performance requirements while the fill shapes are added. Foundry fill requirements are met while preserving timing correctness and minimizing the impact on dynamic power. (Source: Blaze DFM)

In this way, the fill insertion tool works in concert with the CMP model in the analysis engine. The CMP model refers to the empirical model that the foundry puts together to predict the behavior of their CMP solution on a given layout pattern. “So if you feed a layout into it, it will tell you what the 3-D topography will look like based on the CMP system, slurry, etc.,” Reed said. “This tells us if the fill is good or not. So if the model tells us we're out of spec for wafer smoothness, for instance, we can change the fill solution to meet the spec.”

The company's first product, Blaze MO, worked from the design to manufacturing side, and mainly served digital designers. It analyzes how the design uses each transistor and then selectively modifies the CDs slightly to make marked improvements in timing, leakage or leakage variability.¹ Blaze IF is a broader, whole-chip solution that works on the design and manufacturing sides and addresses all products from DRAMs to image processors. It supports all modern CMP design rules, including allowed density upper and lower bounds, density smoothness constraints, dummy via insertion, dimension constraints and pattern types for dummies, dummy-to-dummy spacing, and spacing between dummies and function trenches or wires, based on the planarity requirements for the interlayer dielectric over the metal.