Superlattice Channel Addresses Gate Leakage

Robert J. Mears, inventor of the erbium-doped fiber amplifier (EDFA) that helped enable the broad-band Internet, was working on finding a way to combine optical devices and waveguides in silicon when he came to an interesting conclusion: Silicon superlattices could be constructed in such a way so as to boost current in one direction, but impede it in the other. The result is a new channel replacement technology that is, in some ways, similar to strained silicon technology, in that dopants are added to modify silicon's band structure. In this case, though, current is enhanced in the horizontal direction (drain current) but reduced in the vertical direction (leakage current). The reengineered channel reduces gate leakage by as much as 60% in NMOS transistors and up to 80% in PMOS transistors, while maintaining or boosting drive current for a variety of deep submicron processes.

The technology is being commercialized by Mears through his new Waltham, Mass.-based company MEARS Technologies , of which he is founder, president and CTO. “The explosive growth of cell phones and other personal electronics devices has created conflicting demands for semiconductors with increased performance and reduced power consumption,” Mears said. “The ability of the industry to respond to these demands continues to depend on the electrical properties of a single material — silicon. As chipmakers attempt to squeeze more performance out of their transistors, the fundamental properties of silicon and its native oxide have become the limiting factor. And while some approaches have been successful in addressing performance requirements, power issues continue to exist. Through a new approach to silicon engineering, we are able to alter the properties of the silicon to improve the power efficiency and speed of transistors manufactured using deep submicron process nodes, such as 65 nm, 45 nm and beyond, while maintaining compatibility with standard CMOS manufacturing equipment that is used for the vast majority of today's semiconductors.”

A main advantage of the technique — which Mears is calling the MST (Mears Silicon Technology) “platform” — is that it is fully compatible with semiconductor manufacturers' baseline processes, whether bulk CMOS, strained silicon or silicon on insulator (SOI). MST Generation 1 is a channel replacement technology incorporating a silicon laminate — or “superlattice” layer — that requires no new materials to be used in the fabrication process. It is employed as a blanket film on bare wafers deposited by an ASM tool, much like standard epitaxy.

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