Metrology Meets Next-Generation Challenges — Barely

Next-generation metrology faces many issues, not the least of which are the complexities of the etch structures being created and considered for 45 and 32 nm. Next-generation transistors will have considerably more vertical structures — finFETs, for example. These involve complex etch shapes to wrap the gate around the channel. Another important facet is the introduction of new materials and how they react to one another and to traditional ones already in use. High-k dielectrics will bring their own helping of headaches.

Metrology OEMs must provide the capability to measure these complex profiles with structures that provide challenging metrology problems. “They’re too complex for scatterometry to work easily, AFM is too slow, and alternatives are being sought,” said Michael Gostein, technology director at Advanced Metrology Systems (Natick, Mass.). Some of these solutions will be needed soon. The requirement is emerging to measure 3-D devices inline, non-destructively.

Gostein sees potential solutions to the 3-D etching problem. “There are new ways to measure these 3-D structures. For example, with infrared light, wavelengths are long compared to the structures, allowing simpler measurements. Therefore, it becomes possible to measure things like etch depth without so much complexity in the spectral response. The process engineer doesn’t have to worry about so many different parameters to interpret the measurement.” There are trade-offs to this approach, but engineers in high-volume fabs may want to simplify processes and get data faster for more wafers.

“There’s also added interest in doing composition measurements on product,” Gostein said. Fab engineers are leaving the concept of performing tool verification or taking a blanket wafer and putting it through an X-ray fluorescence (XRF) unit. They want faster feedback. This is partly driven by the single-wafer processing trend.

Measuring by layer

There is not enough focus on the fact that complex structures are the result of a series of operations and processes. “Engineers tend to look at the final product and say, 'I want to measure everything.’ Often, that cannot be done,” Gostein said. “However, if you look at the individual process steps in a sequence, it’s possible to generate information at multiple steps that can be fed forward to the next metrology step. This allows a complex problem to be broken down into simpler problems.” By the time the final device is complete, much information is available from the process history.

This is routinely being done. Focus is on ways to feed forward information from previous steps and simplify metrology by looking at fewer variables, but measuring them more often. If a particular OEM’s tool is not practical for a measurement, specialized tools can be used to obtain data for the final models. This entails taking a complex problem and breaking it down into a simpler one. There is no attempt to solve the entire measurement problem in one sweep; the answer is arrived at in discrete pieces. Dedicated tools and a better information infrastructure are replacing the once-lauded Swiss Army knife platform approach. One measurement can be fed to other tools to do the job.

Inspection and modeling

Mike Kirk, vice president of the wafer inspection group at KLA-Tencor (San Jose), observed that they are collaborating with their users’ R&D operations for 45, 32 and now 22 nm development. “As they develop the process, they’re bringing in metrology as never before,” he said. “They work with our physicists and mathematicians to model what a 20 nm defect looks like in a 32 nm trench next to five different materials and, if the defect is a dielectric, how it scatters light. We build these models and then do the same with e-beam inspection. Then we model how overlay variations, coupled with LER, can affect the measurement.”

This takes place as material choices are being made. “Before, there would be proof of concept, proof of design for the transistor all the way down to first interconnect. Then we’d be told what the problem defects or difficult measurements were. They now realize that’s too late,” Kirk said. For immersion lithography, KLA is engaged in several interactions with users, paretoing immersion lithography’s defect mechanisms, as well as doing a systematic study of the metrology — overlay in particular, but also some optical CD.

1. The processing of next-generation structures requires new platforms, such as this overlay metrology system, which addresses the unique risks of patterning yield from overlay errors in advanced lithography, including the combination of increasing pattern density plus 193 nm immersion lithography methods. (Source: KLA-Tencor)

It is not cost-effective for anyone to make a point product for a specific immersion lithography process. If, in the course of developing an immersion lithography process, the resist or resist’s topcoat must be changed, this can change optical properties, rendering a single wavelength of inspection as non-optimal. It would then require another tool. Like other OEMs, KLA has re-engineered its image computer and algorithm coding to make them flexible and quicker to implement. The optics are designed for flexibility and extendibility: broad-band illumination (<266 nm to visible wavelengths), high numerical aperture (NA) at all inspection pixel sizes, and variable apertures for illumination and collection that block the “noise” generated by the wafer’s natural background variability.

The notion is changing that measuring one spot on a wafer gives a solid metric for where the process is. Parameters vary within the wafer and the die. Because atomic layer deposition (ALD) and line roughness variations have become critical, control across the wafer and die is necessary. The dichotomy of random vs. systematic defect is evolving into a concept such that what typically is called a random defect is really a systematic defect for which, as yet, there is no solution.

The lithography defect dilemma

Major hurdles are posed by immersion lithography, double patterning, and lithography process qualification. These elements will profoundly affect advanced metrology at 45 nm, and definitely at 32 nm. What will happen at 22 nm is cloudy; much will depend on what kind of lithography is used. For 45 and 32 nm, there is little doubt it will be immersion lithography and double patterning.

Yogev Barak, chief marketing officer for the process diagnostics and control operation of Applied Materials (Rehovot, Israel), sees immersion lithography’s biggest problem to metrology in the defect area. “Placing a liquid between the lens and the wafer brings a whole slew of new defect types,” he said.

2. Small partial bridge between extremely dense structures. Shown here is a 65 nm line grating patterned with an immersion lithography tool. (Source: Applied Materials)

Applied’s UVision inspection tool uses a deep ultraviolet (DUV) wavelength laser close to that of a stepper. This optimizes its inspection sensitivity on resist layers, partly because of the fact that the bottom antireflective coating (BARC) absorbs most of the DUV light. If different wavelengths were used, there might conceivably be reflections of the light through the antireflective coating (ARC), hence creating noises from underlayers. This effect is minimized by DUV wavelength. It is also possible to use small pixel sizes with the DUV laser, enabling the detection of infinitesimal 30 nm bridges or protrusions in the resist structure.

Double patterning seems to be the only early path open to 32 nm. Stepper and metrology OEMs must work together to solve its problems. From a metrology perspective, overlay is fundamental. With double patterning, overlay errors translate almost directly into CD errors. Stepper manufacturers must dramatically improve the overlay budget. One emerging approach to address this issue is using CD-SEMs to measure overlay errors and reporting them back to the stepper for process control.

New materials and design

When materials used by device manufacturers change significantly, normal, safe design rules are off. “One must start from the beginning, not just map out the process space for those particular layers,” said Tony Edwards, vice president and general manager for the nanoelectronics division of FEI Co. (Hillsboro, Ore.). “This brings a new level of focus to integration and understanding how the process for one step is sensitive to prior layers, and how integrating multiple materials causes additional complexities and may require fundamental systematic evaluation of areas such as interdiffusion, stress, and everything else for which there were rules of thumb.”

New materials are creating unexpected interfacial and diffusion problems. Diffusion can occur with carbon concentrations across the ultralow-k dielectrics. Also, new films can have different adhesion qualities sensitive to cleans.

Then there are materials sensitive to high-energy beams. Once a material is a fully integrated structure, high-energy beams become less of an issue, and it is possible to obtain significant information from cross-sectional data.

This requires additional failure analysis and process yield defect modes, all of which need TEM analysis. According to Stacey Stone, FEI’s lead technologist for the semiconductor fab group, because integration issues are high-priority, the capability to look at the entire structure and quantify it post-integration and post-manufacture makes it crucial to feed design rules to the process and design groups. “The layers must be integrated together to obtain the desired information,” he said. Cross-sectional information has always been used to evaluate failures and defectivity. It now seems unavoidable on the forward end of the development cycle, where fundamental materials are considered.

Some device makers see a need for integrated information from cross-sections, whether about dual damascene or finFET structures. There is an increased need for structural cross-section metrology. Since state-of-the-art TEM and scanning TEM (STEM) exceed what are deemed to be 22 nm node requirements, the issue is not resolution or calibration; it is whether this process can be efficiently employed to support the fab. It is no longer possible to do construction analysis at the process end — it must be done during development.

Fundamental limits

Sematech (Austin, Texas) and the National Institute of Standards and Technology (NIST, Gaithersburg, Md.) are working to determine where optical CD will hit the wall. This technology is an important inline control parameter, and there are not many good answers — SEM may not be as practical. Most expect this at the 22 nm node, but both organizations are working to determine optical CD’s fundamental limits.

A subset is overlay. Some device manufacturers may experience up to a 10% yield loss from overlay problems — the inability to determine subtle overlay error components. With double patterning, there will be fewer metrology options. “Measuring lateral geometries in the structural space, and even trench depth to some extent, is problematic,” said Sean Jameson, vice president of sales and marketing for Jordan Valley Semiconductors (Austin, Texas). “There are potential solutions with FTIR and some other techniques for the trench. However, fundamental limitations are coming at us in the CD and overlay area.”

NIST and Sematech are attempting to determine reference standards for CD and overlay control using atomic force microscopy (AFM) as the absolute reference to identify error components. There are obstacles on the metrology road, and some of these deal with fundamental limitations for SEM and optical solutions. If double patterning does come, its impact on overlay metrology will be significant. Although there are problems with 22 nm lines and trenches, there are solutions — AFM, cross-sectional analysis, etc. — but not for overlay.

Metrology for characterization

Jameson sees a significant trend toward the adoption of X-ray technology. “In the gate stack space, there’s an obvious blend of metals metrology and opaque and transparent dielectric metrology measurements. These limit current technologies; metal gates will be thin, creating problems for some current metal metrology solutions. In the high-k space, there are problems for optical measurement tools.”

Even with gate capacitor stacks in DRAMs — these high-k dielectrics and interfaces used to be ONO, but now are more likely hafnium, halfnium aluminum oxide, often ALD films. Refractive indices are similar, and these methods cannot separate them. Likewise, on the logic side with high-k over the residual oxide, optical methods cannot separate them — again — because of refractive index similarities. “Aside from some electrical solutions, as 32 nm comes into play, X-ray may be the only solution for characterization,” Jameson said. Not too far beyond 32 nm, optical will have problems, even in the optical CD space.

Thickness is not the sole issue; material properties are a growing concern — whether density or interface roughness, or even diffraction properties: texture or grain. Silicide transitions are an example. As the industry transitioned from tungsten silicide to working with nickel silicide (NiSi), phase became a problem. Heavy metals, such as platinum, are added to NiSi to stabilize the phase. Even the phase in TaN barrier films has shown strong correlation to copper grain orientation and texture, which can impact electromigration.

Some metrology technologies, for thin films for instance, can be extended by going to shorter wavelengths — to vacuum UV (V, 153 nm and below), enabling improved resolution. “Scatterometry’s already a natural extension of conventional thin-film metrology, spectrophotometry- and ellipsometry-based,” said Bents Kidron, marketing director at Nova Measuring Instruments (Rehovot, Israel). “Combined with modeling based on rigorously coupled-wave analysis, it can meet 3-D measurement needs for complex structures. In-die measurements will be required, as scribe line test sites do not always correlate well with actual results on real structures.”

Not all optical metrology techniques may require extension to be effective in the very thin film domain. For example, Verity Instruments (Carrollton, Texas) is developing a technology using heterodyne interferometry to measure ultrathin gate dielectric films. This approach has shown potential to exploit visible heterodyne techniques in a reflectometry mode to measure ultrathin films with a corresponding improvement in measurement resolution to <0.10 Å (Fig. 3).

3. The heterodyne interferometry approach to measure extremely thin films uses a single wavelength at fixed incidence angle. Measurement dynamic range is >0-1000 Å. This range can be extended by switching source wavelength. Unlike ellipsometry, extreme thin film reflectometry (XTFR) can measure thickness directly. Measured resolution is ~0.08 Å. (Source: Verity Instruments)

In parallel, Nova expects new metrology capabilities based on X-ray techniques — primarily X-ray reflectivity (XRR) and X-ray diffraction (XRD) — to evolve. “XRD will be more useful when not only geometrical parameters are measured for process control, but also structure, composition and texture will be critical for reliable and repeatable processes and devices,” Kidron said.

Greg Wolf, director of new technology development at Rudolph Technologies (Flanders, N.J.), views metal gate as a good field for picosecond laser sonar applications. “It can simultaneously measure metal or silicide phase and thickness,” he said. “Fully silicided metal gates are the pathway to full metal gates, so the thickness and phase of metal or silicide are important process control parameters and are measurable on product with picosecond ultrasonic technology. When the industry transitions to full metal gates, a monochromatic microspot XRF tool can measure the alloy composition for metal gates. Thus, the combination of Pulse and MMXRF allows complete process control for metal gates. So we’re concerned about thickness, phase and alloy composition, which allows process engineers to tune, then control work function for required device performance [Fig. 4].”

4. Ultrasonic technology can analyze material type and thickness. Plotted here is the optical signature of the electron-phonon interactions measured at the film surface during the first few picoseconds as it dissipates the energy deposited by a femtosecond laser pulse. Plot-line color indicates material type, and multiple traces are films processed at different temperatures. The signal differentiates the films by phase. Later portions of the same signals (not shown) have the acoustic response, which provides information about layer thickness. This dual capability derives from the high bandwidth (terahertz) of the time-evolved signal, permitting different parts of the spectrum to carry different types of information. (Source: Rudolph Technologies)

From a technical point of view, 32 nm metrology will not be that different from 45 nm. It may be somewhat more expensive to do, but it definitely is doable. However, at 22 nm, everyone’s crystal ball seems to get cloudy, and suppliers cannot even guess whether something radical will need to be done to extend (or develop) the necessary technologies.

However, if past performance is any indication, the future is doable.