Executive Roundup: How Fabulous Will 2007 Be?

In 2006, the semiconductor equipment market enjoyed a 25% growth, largely fueled by spending for memory fabs. Will 2007 follow suit or turn out to be a correction year? Here's what some industry executives expect. This online version includes comments from an expanded list of executives.

Staff -- Semiconductor International, 1/1/2007

Tim Archer
Senior Vice President, Dielectrics Business Group,
Novellus Systems Inc.

Consumer demand for smaller, slimmer cell phones and other portable devices that require more functionality and higher-density memory storage in smaller form factors is driving semiconductor manufacturers to consider new design and manufacturing solutions. Thinner multi-chip packages (MCPs), systems-in-a-packages (SIPs) and packages on packages (PoPs) that contain more layers and functionality are important advances in the quest for continued convergence. MCPs of up to 16 layers are now being realized, and this is only the beginning.
 
New technologies are needed to create these packages, including new laser sawing and drilling techniques, as well as adhesives and deposition technologies. Deposition of a conformal oxide in high-aspect-ratio features can be used to insulate the sidewalls of through-silicon vias for 3-D SIP integration. Traditional plasma-enhanced chemical vapor deposition (PECVD) requires temperatures higher than typical photoresist and back-end-of-line (BEOL) wafer passivation coatings can tolerate. Atomic layer deposition (ALD) can be performed at lower temperatures, but deposition rates are very slow, leading to high packaging costs, which may be prohibitive for the consumer market.

Enabling new packaging solutions will require deposition tools that can deposit conformal films in very high-ratio features while overcoming the limitations of PECVD and ALD. Key elements of these tools will be tolerable processing temperatures and high deposition rates for increased productivity.

Wan-Thai Hsu
CTO
Discera Inc.

In 2007, we expect to see the convergence of three key trends. The first trend is a mandate for scalability driven by electronics manufacturers' desire to deliver multi-functional products. A second trend is the realization for a solution to help the bottlenecks in time and cost in moving to the smaller nodes of 45 nm and below. These two trends will drive the third trend — the industry's readiness to adopt alternative approaches to semiconductor design, with one of the key alternatives being MEMS.

This makes for an interesting period in the semiconductor industry over the next few years. 2007 will be the first year of visible changes taking place with the emergence of high-volume MEMS devices, and this will continue to grow as a technology as it further matures, bringing down size and costs without necessitating a migration to expensive geometries.

Sven Lofquist
President & CEO
Micronic Laser Systems

In 2007, maskmakers will begin to gear up for 45 nm, and the new wave of advanced photomasks will be fundamentally different and more demanding than anything seen before.

Optical proximity correction (OPC) and the design-to-mask transition grow more demanding each month. Phase-shift technology is moving into wider use. Extreme ultraviolet (EUV) and double-exposure techniques are coming under intensive study. Each of these developments creates new issues for mask producers, but one important point cuts across all of them: Resolution is no longer the only important factor in the advanced mask-writing process.

Economics are the underlying driver of the entire semiconductor industry, and leading maskmakers are already sounding public alarms about skyrocketing write times. Moreover, mask critical dimension (CD) control is tightly linked to device yield and binning, and traditional writing methods have difficulty with molecular-level accuracy. Pattern registration on the mask blank is also emerging as an important yield consideration, especially for the double-shot techniques that seem increasingly likely to be needed.

Successful developers of mask-writing equipment will advance their technology to provide well-balanced and economical packages. The time is ripe for reconsideration of traditional ways of doing things. The next few years will be very interesting times for maskmakers and their equipment suppliers.

Marc Heyns
Department Director & IMEC Fellow
IMEC

The importance of ultraclean processing in the fabrication of microelectronic devices has been recognized since the dawn of solid-state device technology. In addition, the challenges in keeping wafer surfaces clean grow with each shrink in feature size, and they have never been so high.

Many new materials are currently being introduced that pose new issues with respect to contamination control and metrology, and require a different type of cleaning and chemical (surface) conditioning than the ones currently used. In many applications, new and sometimes much more vulnerable materials are introduced, often resulting in degraded cleaning selectivity. Removal of photoresist and residues without damaging or etching of the underlying materials is becoming very critical for future generations of devices. During front-end-of-line (FEOL) ion implantation, the photoresist becomes substantially hardened and difficult to remove, without noticeable substrate loss. After back-end-of-line (BEOL) etching, the selectivity of removing resist and residues with regard to removing low-k and without degrading the dielectric properties is very challenging.

Another major challenge is the removal of nano-sized particles in the sub-30 nm range that will become yield killers in aggressively scaled technologies. These particles must be removed in various parts of the process and on a variety of materials and structures without significant material loss or roughening, especially for the silicon substrate, and without generation of damage to the fragile structures, such as aggressively scaled STI features and gate stacks.

However, despite all these challenges and the ongoing efforts to tackle them, the (lack of) production-worthy solutions to many of these issues can still be considered a hidden International Technology Roadmap for Semiconductors (ITRS) roadblock. If we want to move full-speed ahead in bringing next-generation technologies to the production level, we should enlarge the awareness that advanced cleaning and surface conditioning solutions for all steps of the IC production process are urgently needed, and more focused attention should be given to some of these major concerns.

Dwain Aidala
President & COO
sp3 Diamond Technologies

As I look ahead to 2007, the biggest trend I see that impacts us and many of our peers is the influence of the consumer on technology. Consumer products are rapidly becoming the platforms that drive technology development. This is the case in high-end processors, which are driven by the continued performance levels from each generation of dedicated game machine or gaming-oriented PC. Cameras and music/video players are driving the flash memory market, which has surpassed DRAM as the process technology driver. Even the communications market is being driven by the consumer, not the business applications. WiFi, Bluetooth, 3G and now WiMax are all evolving and seeing significant financial investments funding new technology solutions in order to address consumer applications. And, of course, the large screen TV market is now driving new processing and technology development in the LED and laser markets as suppliers of these devices attack this large and growing consumer market.

What does it all mean? For many it means opportunity. For others, it means being passed from behind by new technology solutions. The challenge is how to address these changes, which have six-month product cycles, and still make money for our stakeholders. Good luck to us all.

Stefan Schneidewind
CEO
SUSS MicroTec AG

After an excellent 2006, we are expecting a relatively stable 2007 for the equipment industry as a whole. Investment in innovative back-end processes, for example, will continue to grow. Tighter pitches, smaller bumps and not to mention looming lead-free regulations are all calling for completely new packaging technologies — ones that can flexibly react to ever-changing market demands. Shrinkage is also causing the industry to seek new materials to overcome challenges, such as thin gate oxides. A neglected technology, wafer-level reliability testing, is making a comeback so these new materials can be tested early in the development cycle — although now at 300 mm. 3-D stacking is also an area we are watching with keen interest. The jury is still out on whether full-wafer or single-chip stacking will become the dominant process. Along with 3-D stacking, two further growth markets for wafer-bonding technologies are the silicon on insulator and MEMS markets, where we expect to see double-digit growth in and well beyond 2007. More and more MEMS applications are finally showing signs of commercialization and, in this sector, the equipment industry will see large demand for high-quality production tools that can improve yield and also for the test tools that can monitor this yield. These tools will be tantamount to the MEMS industry's commercial success.

Rick Wallace
CEO
KLA-Tencor Inc.

With the consumer electronics economy driving more and more chip production, the tremendous risk of missing market windows is rapidly increasing the value of a fab's yield ramp. Chipmakers are realizing that fully utilizing the latest generation of inspection and measurement tools cannot only fine-tune production, but can also shorten development time. We are seeing inspection and measurement incorporated into advanced process development, and even into design. The key is proactively leveraging yield knowledge early in the development cycle.

The combination of high market risk, atomic-scale features and new chip manufacturing technologies is driving a shift to new and more proactive yield control methods. The ability to apply the most advanced yield learning to all levels of production is emerging as a key differentiator in determining fab profitability. Early partnering is critical for customers to maximize their yield and be market ready.

Alec Babiarz
President, Business Development
Asymtek

Manufacturers of handheld electronic devices have realized that most CSPs require secondary underfill. This is because there is not enough mechanical structure in the devices enclosures in today's smaller and lighter products to prevent board flexure and stress on CSPs when they are dropped (Aren't you relieved when your cell phone keeps working after you drop it?) This reliability requires more secondary underfill and manufacturers demand high throughputs; jetting is the way to apply that underfill most effectively. As a result, we see that jetting is becoming a necessity in CSP lines.

Discretionary income affects the demand for consumer electronic and handheld devices. If there is a drop in spending, there could be a drop in consumer electronics, reducing demand for our industry's products. The good news is that there will be more consumers in China and India. Outsourcing to those regions will grow their economies, their citizens' disposable income, and consequently their demand for more products. American products will help fulfill that demand, and a lot of the local markets will be supplied by local manufacturers of brand products. For equipment suppliers, it means we need to develop more support, services and infrastructure in developing countries.

Don Mitchell
Chairman & CEO
FSI International

IC manufactures are facing enormous technical and economic challenges as they focus on ramping 65 nm production, while achieving yield and device performance goals, controlling costs and meeting schedules. As a supplier, therein lies the challenge and the opportunity.

As much as possible, 65 nm processes have been developed and qualified on existing platforms, allowing IC manufacturers to utilize production-proven systems. This mitigates the risk of meeting installation and ramp schedules, reliability issues, and also minimizes investment in spares, logistics and training. Moreover, whenever possible, technology extensions should be offered as field upgrades for new product development and existing fab advancements, which allow IC manufacturers to utilize current capital. To further improve cost of ownership, equipment suppliers need to continue optimizing tool capabilities, such as material handling, to provide throughput improvements without the expense of having to requalify entirely new platforms or processes.

Surface conditioning at 65 nm also represents an inflection point where cleaning and wet etching processes have been reengineered and optimized to reduce material loss, while still removing unwanted films and contaminants.

Phil Blakey
US President, Semiconductor
BOC Edwards

The emphasis for 300 mm fabs is shifting from making the process work to reducing ongoing costs. This presents an important strategic opportunity in 2007 for products and upgrades with benefits such as improved efficiency or reduced utility and environmental costs. Often these are not what might be considered “first order” benefits. They are not obvious or dramatic in their initial impact, but rather they accrue slowly and steadily over the long term. Demonstration of these benefits, and justification of capital expenditures to obtain them, is a data-intensive process that requires deep technical understanding and thorough process characterization. Proactive investment in acquiring this data is an essential component of any strategy to capitalize on these opportunities.

Consider emission management of PFCs and other fluorine species — an area of intense public interest today because PFCs are a primary contributor to global warming. The conventional approach simply combusts the offending agents, then scrubs the combustion gases. Problem solved? Possibly not. The gas emission problem may be gone, but what to do with the liquid effluent? A liquid abatement solution can concentrate the fluoride into a form that is safely and easily disposed, while the bulk of the water is recycled. Each component of the combined solution has associated costs that must be thoroughly characterized in order to provide customers with a convincing economic solution.

Reductions in ongoing costs, such as utilities and abatement, will continue their emergence as primary purchasing influences this year and through the foreseeable future. Successful suppliers will provide products that address these concerns, and will also provide detailed analysis of costs and benefits to support their positions.

Roy Prasad
President & CEO
Invarium Inc.

The economics of chip design are changing. Over the past five years, we have seen a large push from the EDA side toward design for manufacturability (DFM). With design costs exceeding $25M per chip, the risk of failure in light of ever-increasing design and process complexity is forcing us to rethink our strategies from defect-limited to feature-limited yield. White space management means different DFM layout enhancement strategies are now competing for the same real estate.

The biggest challenge going from 65 to 45 and 32 nm remains in lithography. One of the more promising approaches in defying the fundamental laws of physics is double-patterning technology (DPT). Decomposing the pattern into two less critical exposures allows us to take advantage of current manufacturing infrastructure and materials, but requires a modified scanner platform.

A full integration of the printing process from design through mask to fab is shifting the focus from traditional optical proximity correction (OPC) to patterning synthesis. Patterning synthesis brings together all parties involved to address flow requirements in the image-splitting process that leads to easy, transparent and migratable conversion algorithms. A cohesive DFM strategy like patterning synthesis optimizes for a better whole.

Today, DPT is technically feasible and part of the optical extension roadmap for dense, regular patterns like flash, which is driving the technology roadmap for the foreseeable future.

Jim Guilmart
Senior Vice President, Global Semiconductor Marketing
Advanced Energy Industries Inc.

One indisputable trend within the global semiconductor industry is the growing focus on expansion opportunities in adjacent markets — specifically solar and FPD. SEMI itself sponsors photovoltaic tracks at SEMICON shows, in addition to hosting regional FPD events.

Indeed, the industry's growing focus on adjacent markets makes both technological and economic sense. Up and down the semiconductor food chain — from OEMs through subsystem and component suppliers to end users — we have enormous thin-film manufacturing expertise that has proven largely straightforward to transfer across to these adjacent markets. For example, arcs occurring in plasma thin-film manufacturing used to routinely diminish film quality and yield. But today, arc-managing technology has all but eliminated yield-crippling arcs not only in semiconductor manufacturing, but in solar cell and FPD manufacturing as well.

However, while pursing these “natural” adjacent markets is necessary, it is not sufficient to sustain long-term profitable growth. The real focus must remain unwaveringly on the needs of our customers — their current needs as well as the emerging ones. We must leverage innovation — in technology, services and ideas — to give customers an advantage. Long-term profitable growth is the result of sustained, mutually relevant partnering with customers in whichever markets they serve.

Ardy Johnson
Vice President of Marketing
Rudolph Technologies

The semiconductor industry, always ripe with technical jargon, has historically moved from buzzword to buzzword. It's not that one topic becomes less important, but rather a new point of sensitivity emerges. There was the era of “tool interfaces” that later became “tool integration.” There was the emergence of cost-of-ownership vs. tool price as the primary economic consideration. Tool “throughput” evolved into “overall productivity.” Now, driven by the advent of immersion lithography, increased sensitivity to thermal and physical dynamics at the edge of 300 mm wafers, challenges created by new exotic materials, and the ability to do sophisticated classifications, the buzzword of today is “defectivity.”

As always, the ever-changing, complex manufacturing variables continue to challenge engineers to create new robust processes, as well as to enhance the performance and productivity of existing processes. Partial sampling strategies for inspection and measurement will likely remain the method of choice where sufficient information is provided. But, the increased value of larger wafers and the proliferation of defectivity modes is stimulating interest in 100% inspection — every wafer, every time. If this indeed becomes the next production trend, the ramifications to yield management equipment suppliers will be significant. One aspect may be that integration of metrology and control capabilities into process tools finally gains significant momentum. In the case of standalone toolsets, throughput, lot scheduling, modularity, flexibility, and multiple steps per fab automation drop will all receive increased emphasis as they are incorporated into the cost-of-ownership models for inline inspection and metrology equipment.

These are trends we expect will grow in prominence as demand for denser sampling increases, and inspection and measurement become more tightly integrated with production processes.

Nick Konidaris
CEO & President
ESI Inc.

I believe 2007 will prove a fertile growth environment for semiconductor equipment manufacturers focused on remaining agile and innovative. A key reason for this is the current industry expectations for DRAM market growth, which will be largely driven by the upcoming launch of Microsoft's new Windows Vista operating system. In concert with this expectation, an iSuppli industry analyst forecasts DRAM market revenue growth of 20% for 2007. Additionally, global consumers continue to drive the insatiable demand for electronic devices that deliver increased functionality and are faster, sleeker and available today…or sooner. Given all this, I believe the opportunity for growth is significant.

At the same time, changing market conditions may require customers to adjust their product lines/roadmaps along a shifting continuum between the cost of ownership and technology advancement. This dynamic environment requires real-time solutions for customers' shifting technology roadmaps, which require changes in equipment, processes and materials. An example of the dynamic market conditions is the increasing number of questions that arise with regard to how the industry will continue on Moore's Law. I believe the success formula for equipment companies in 2007 is to marry a comprehensive product portfolio with a nimble business model, and continue actively investigating new markets and applications that may reap substantial benefits from their core technologies.

Chris Moore
President & CEO
Advanced Metrology Systems

We continue to see the semiconductor metrology market dividing into more market segments split by application, technology and, more significantly, customer metrology strategy. With the expansion of end-user markets other than the PC, such as phones and PDAs, solid-state storage, and automotive, our customers have had to adapt to more flexible manufacturing strategies while increasing their overall fab utilization and fab capacity — all with fewer people. This ongoing process is leading to a higher degree of specialization in all areas of the industry.

As we shift to supporting different customer metrology strategies, we find that measurement problems cannot be solved in exactly the same way for each customer. Thus, there is a need for increased application support and a flexible applications and technology approach. We expect this trend will strengthen through the next few years.

John Odom
President
EKC Technology
DuPont Electronic Technologies

The global economy is showing great resiliency, and I am quite optimistic about the growth prospects for the semiconductor industry in 2007. An estimated 50% semiconductor demand is now driven by consumer-purchased electronics. If energy prices, interest rates, and other factors that impact discretionary consumer spending remain in check, 2007 could be another outstanding year. Inventories in the semiconductor value chain have been building and have reached worrisome levels. This may result in a correction in the first quarter. However, the anticipated launch of the new Microsoft operating system in early 2007 should drive significant new device demand for processors and memory. I believe any correction will be short-lived.

Our focus is advanced cleaning and residue removal, and opportunities in this market are particularly exciting and challenging. Layer counts and cleaning steps are increasing rapidly for advanced semiconductor devices. Factors such as the introduction of sensitive porous low-k dielectrics and lower material loss tolerances associated with shrinking CDs are driving a need for highly selective and robust cleaning processes. And quality requirements in terms of particles and trace metal ions will become more demanding. For advanced integration schemes, cleaning solutions are increasingly vital to the success of the wafer fab, and this is creating significant opportunities for innovation.

Tony Edwards
Vice President & General Manager,
NanoElectronics Business
FEI Co.

As devices continue to shrink, they and the processes that produce them become increasingly difficult to measure and control. The industry currently finds itself at a crucial transition in imaging and measurement technology. Much as scanning electron microscopy (SEM) replaced optical microscopy as the primary metrology tool more than a decade ago, SEM is now being replaced by scanning transmission electron microscopy (STEM), as SEM approaches its own resolution limitations. As always, the ultimate drivers for technology replacement are economic. In this case, the need is for reliable data to support process development and control decisions that shorten time-to-market for new products and improve yields in high-volume production. Filling this role requires more than imaging resolution, it requires quantitative, repeatable, statistically significant (i.e., high-volume), gauge-capable data.

The latest-generation STEMs can routinely provide sub-angstrom resolution that is more than an order of magnitude better than the best SEM. However, time-consuming sample-preparation procedures, difficult instrument operation, and high cost have impeded STEM's acceptance for process control applications. Solutions to both of these impediments are available.

Focused ion beam (FIB) based sample preparation can be automated and can produce high-quality, location-specific, thin samples of consistent quality in a fraction of the time required by conventional manual techniques. Current-generation STEMs have been optimized for system stability, and setup and operational procedures have been greatly simplified, allowing them to be highly automated as well. Together, these technologies offer the prospect of completely automated STEM-based CD metrology with throughput and time-to-data sufficient to meet the demands of process development and control — with a cost per sample that is comparable to conventional high-resolution SEM.

Farhad Moghadam
Senior Vice President
Applied Materials Inc.

Global economic expansion is likely to continue in 2007. Strong recoveries in European and Asian economies continue to support this growth. Global real GDP is estimated to have grown 3.9% in 2006, compared with 3.5% in 2005. The forecast for 2007 worldwide GDP is 3.2%, according to Global Insight. However, declining oil prices and steady interest rates could help spur consumer spending.

The electronics market remains a healthy sector. Our assessment based on several factors leads us to believe that 2007 growth will be ~5%, same as in 2006. The consensus view is that mobile PC sales will continue leading PC growth with ~22% growth in 2007. The mobile handset market is expected to increase 10% in 2007 to about 1.07B units. Flat-panel TVs and flash-based portable media players are high-growth segments of the consumer market, with strong forecasts for 2007.

These drivers are expected to result in a growth of 10% for semiconductor sales in 2007 according to the Semiconductor Industry Association (SIA), which is roughly flat with 2006 growth. The wafer fab equipment market is estimated to grow ~5-10% this year, after a strong expansion of ~25% in 2006, with memory spending leading the way.

Capital equipment spending will also be driven by the need for technologies to address current IC lithographic patterning limitations, strain engineering solutions to improve drive current, and critical new technologies such as high-k metal gates and copper contacts for scaling to 45 nm and beyond. With these continuing engineering innovations, Moore's Law remains on track. Future nanomanufacturing complexities, however, pose daunting challenges. R&D conducted in the coming years promises to be very exciting.

Joe Cestari
CEO
ILS Technology

We're now seeing the first of many new waves of innovation in the way remote access technology is used by companies in global semiconductor manufacturing. Companies are improving their operating margins every day through the use of this technology, and they are seeing a drastically lower cost of entry through the software as a service model, which this industry has not witnessed before. Real-time connectivity enables companies to acquire and track mission-critical data from different technology partners, customers, suppliers, field engineers and sub-contractors scattered around the world. Remote access technology was originally designed to enable equipment OEMs to service their tools at remote locations just by logging on to a computer in the home office. Now, OEMs can monitor the manufacture and assembly of their own tools, and chipmakers can make improvements to their designs from the instantaneous flow of information coming from products in the field. While remote access technology initially addressed tactical issues, it has evolved into something more strategic, providing companies with real competitive advantages.

Timothy P. Tobin
President & CEO
Entrepix Inc.

Since semiconductors have proliferated to most aspects of our everyday lives, there is less of a dependence on any specific market segment or product than was historically the case. Consequently, a new phase of industry maturity has evolved, one that is characterized by more stable and controlled growth. In such an environment, technology alone, which has traditionally been the cornerstone of the industry, cannot drive acceptable financial results. Operational excellence, risk mitigation and ultimately accelerating time-to-revenue are three vital components that manufacturers must optimize.

This has led to an openness and true partnering between suppliers and customers. There is a clear shift in the thought processes and considerations of manufacturers who now look to such partnerships to increase their competitive advantage and maximize financial returns. This collaboration is fortunate for both technology advancement and economic benefit, particularly as it relates to the fast-growing and increasingly complex world of chemical mechanical planarization (CMP).

In general, technical trends for CMP processes are driving toward the lowest possible downforce and least possible shear. Achieving this requires cooperation from consumables suppliers, OEMs and engineering teams in the fab. Only through this collective effort can processes and materials systems be developed that will meet all required manufacturing metrics for performance, reliability, repeatability and cost.

A secondary trend that is emerging in CMP is the adoption of many non-traditional polishing applications that enable the manufacturing of such products as MEMS, high-aspect-ratio power devices, advanced packaging, and alternative substrate platforms. As niche applications that have not historically required CMP, these manufacturers are increasingly looking to external partners for technology integration and production outsourcing, as it offers the quickest and most certain path to bring products to market.

André-Jacques Auberton-Hervé
President & CEO
Soitec

The year will be marked by expanding, high-volume silicon on insulator (SOI) production. Our customers are experiencing strong acceptance of their SOI-based products in the PC and server markets, and are now increasing the drive into consumer markets.

The transition to 65 nm SOI CMOS, which can further decrease cost-of-ownership, will accelerate. Other growth areas abound as well — look for RF applications, more products for the vast automotive markets, and the debut of a new wave of SOI-based photonics. For players in the III-Vs world, there is a new generation of cost-effective engineered substrates.

SOI technology decisions for the 45 nm node (including strained, ultrathin [UT] silicon and UT buried oxide) will be refined. Embedded and floating-body memory technologies will move to the forefront.

With all this activity, we see enthusiasm, energy and momentum running high throughout the SOI ecosystem.

Linda Rae
Executive Vice President & COO
Keithley Instruments

A chief driver in semiconductor test continues to be lowering the cost of test, even in the face of continuing device shrinks, increase in number of product die per wafer, ongoing process innovation, and integration of new materials. These factors are shaping test engineering and innovation in a variety of areas.

For example, there is a broad move toward parallel test, which represents a new paradigm for parametric testing. This technique permits more data to be extracted from every probe touchdown. Parallel test allows engineers to choose between increasing wafer test throughput dramatically, or to use the time to acquire significantly more data and gain greater insight into their processes than ever before.

We're also seeing adoption of automated RF testing techniques, and integrating RF test with traditional DC measurements. The need for RF measurements at both the wafer and component level is increasing as the industry progresses toward the 65 nm node and beyond. RF metrology of new devices and materials, along with standard DC parametric tests, allows fabs to control their processes better than with DC parametric tests only.

Adaptive test is another new methodology that involves changing test strategies automatically based on limits used for statistical process control, eliminating the typical delay of waiting for engineer disposition. The typical strategies fabs pursue to lower the cost of test have included testing less, testing more efficiently, testing differently, and/or reducing the cost of the testers used. Adaptive test, however, allows electrical testing to add value to the process by combining efficient testing with the ability to test differently.

Franklin Kalk
Chief Technology Officer
Toppan Photomasks Inc.

As leading semiconductor makers ramp production of 65 nm devices, and the 45 and 32 nm technology cycles come into view, there is wide agreement on the need to continue advancing resolution enhancement techniques (RETs) to extend 193 nm lithography. While phase shifting, optical proximity correction (OPC) and immersion lithography have been evolving for years, industry leaders have recently added double patterning (DP) to their talking points — and to their roadmaps, in some cases.

DP is considered by some to be the most valuable design for manufacturing (DFM) application to date. DP presents photomask makers with a different set of challenges beyond the usual requirements. For DP to become a commercial reality, a photomask maker must have the expertise to determine what controls will be needed for CD and overlay requirements, the experience to work out technical and business challenges for throughput, cycle time, cost and quality — and the financial and technological resources to apply all these elements at manufacturing facilities in multiple markets.

Because the photomask is the contact point between the chip-design community and the semiconductor fab, photomask makers will continue to play an integral role in developing and delivering DFM's potential in 2007 and beyond. At a basic level, this evolution will require more than the collaboration that everyone agrees is essential. It will require, for example, a reliable, fully integrated global network of photomask know-how and production capability that enables designers located anywhere in the world to work seamlessly with the growing number of fabs in Asia securely and in real time.

Isaac Mazor
CEO & Founder
Jordan Valley Semiconductors

One of the biggest technical trends we see is how quickly the flash manufacturers are turning to copper interconnects. Several are already using copper now, and many others have told us that the yields in copper are equivalent or better than aluminum. There's a cost benefit if a company transitions to copper. This savings triggers the DRAM space, where they have to save every penny they can on each die. Once the first DRAM supplier goes to copper, there will be a domino effect; they'll all go rather quickly.

Copper needs a liner to prevent leaking into the dielectric, and these thin, metallic barrier layers cannot be characterized by traditional opto-acoustic metrology — they're just too thin. X-ray metrology is a good solution, because the copper is transparent and the small X-ray wavelengths allow for excellent resolution. X-ray technology has long been accepted on the packaging side for defect inspection, and it is now emerging as a viable inline technology.

I believe we will continue to see the emergence of a variety of X-ray solutions as we move through 2007.

Bob Reback
President & CEO
Cimetrix Inc.

The big messages we hear from chipmakers include trends towards “single wafer,” “virtual metrology,” and the success in using fault detection and classification (FDC) software to improve productivity, all of which require access to higher-quality and finer-granularity data from process and metrology equipment.

The problem is that the costs of using proprietary methods to capture, route and manage the data are high, plus the proprietary approach typically locks you into one vendor. To address this issue, leading ISMI member companies have been promoting a standards-based approach to obtaining this data called Interface A, which should significantly reduce the costs over the long term, while improving the quality of the data. Now that several ISMI member companies have successfully completed Interface A pilot projects, we are starting to see equipment purchase specifications that require the Interface A standard.

We expect that Interface A solutions will continue to be increasingly deployed by chipmakers, and we believe that within three years, most 300 mm fabs will require Interface A on all new equipment, similar to the GEM300 requirements.

Walden C. Rhines
Chairman & CEO
Mentor Graphics Corp.

Electronic design automation (EDA) is becoming more than just a way of improving productivity and quality and reducing time-to-market for the semiconductor industry. Leading electronic designers are finding that simply applying enhanced versions of the EDA industry's traditional tools are no longer sufficient. Instead, designers are choosing to reevaluate their design processes and, in many cases, adopt new methodologies that are enabling companies to make dramatic improvements in key parts of their design flow.

For instance, methodologies including electronic system level (ESL) design and intelligent verification are becoming essential as design complexity steadily marches down in geometries. At 90 nm, EDA tools became critical not just to achieving better, faster, higher-yielding chips, but to achieving them at all. Design for manufacturing (DFM) tools are proliferating at a rapid rate, including some of the fastest ramp of customer usage the EDA industry has ever seen. Looking forward, the intense challenges of 45 nm and below require design tools that enable yield- and manufacturing-aware tools that assist designers in identifying “hot spots” in their designs that are difficult or even impossible for the manufacturing process to achieve. Fortunately, the industry is well on its way.

Kurt Lackenbucher
Executive Vice President & COO
SEZ

The semiconductor industry has grown more mature and its cycles more predictable. We now see many “microcycles” overlapping — for example, when foundries are in a slow period, memories may be experiencing a boom. Or within the memory market, some are shifting toward DRAM, while others are investing in NAND flash. These microcycles can be localized to specific geographies or even driven by specific customers. Ultimately, the trend creates a healthier environment overall.

Wet cleaning is an area of particularly strong focus — the next 18 months will prove to be the inflection point for single-wafer wet processing solutions, which could account for up to 50% of all cleans by 2008.

Mihir Parikh
President & CEO
Aquest Systems

2007 will be an inflection point in the history of 300 mm IC manufacturing. The International Sematech Manufacturing Initiative's (ISMI) 300 Prime effort will provide a path for chipmakers and equipment and automation suppliers to collaborate on maximizing productivity.

The need to address the breadth of “delays” throughout the IC manufacturing process will be the “Prime” focus of chipmakers in terms of improving manufacturing productivity, reducing costs and also being responsive to rapidly changing end-customer demands. Equipment and automation suppliers will have to systematically address such “delays” by optimizing various aspects of manufacturing systems, such as recipe/parameter management; high-capacity, high-speed material handling systems; lot and dispatch scheduling algorithms; variable lot size management, etc. Such optimization will result in improved equipment utilization, decreasing fab cycle time, responsive management of hot-lot demands — paving the way to high-volume, yet flexible fabs with a market responsive small-lot, short-cycle capability.

Adrian Kiermasz
President & CEO
Metryx

In volume IC manufacturing, CMOS is still prevalent, and industry trends in the near-term will (as usual) be governed by shrinking devices, new materials, and process and integration challenges.

Decreasing feature sizes bring more sophisticated devices and/or more die per wafer. As 300 mm wafer production volumes grow, there is a very strong industry trend toward cost-effective, non-destructive metrology for “on-product” wafer measurement. Processed 300 mm wafers are getting ever more expensive, hence the increased trend and frequency in metrology measurement checks. Performing metrology on actual device features eliminates the need for artificial measurement sites and can save cost and eliminate possible sources of error.

Integrated metrology (IM) solutions will continue to be implemented, where it is technically required and makes economical sense. An example of this is the integration of metrology solutions on chemical mechanical planarization tools. There is also a move toward cluster-type metrology tools, incorporating key measurement stations on a single platform.

With all the discussion over IM, it should be emphasized that standalone metrology is strong and will continue to be strong into the foreseeable future. Depending on the customer, fab and technique itself, it simply doesn't make sense to integrate some metrology; because of this, the standalone market will remain strong.

Bruce Hueners
President
Palomar Technologies

For semiconductor equipment suppliers addressing the "final manufacturing" or "value end" of the market, 2007 will see a continued focus on emerging packaging technologies and development of the equipment, features and processes to interconnect these complex devices. These capabilities include custom, low-profile, fine-pitch interconnects via gold ball bumping, unique wire looping for high-frequency devices, and high heat transfer eutectic die attach for high-power LEDs and laser diodes. Equipment manufacturers will be increasingly required to provide complete, precision assembly solutions, consisting of the tools, process recipes and expert support for customers worldwide.

In addition to the given requirement to run a "going concern" in today’s global economy, the ongoing trend of "value chain disintermediation" will require device manufacturers to provide the best quality at the lowest price as packaging technologies mature. Additionally, finer-pitch, lower-profile, thermally dissipative new packages will require rapid, innovative assembly solutions. This provides unique challenges for equipment suppliers who provide the enabling tools to assemble precision microelectronic products. As the customer base shifts from traditional OEMs to specialized device manufacturers, identifying and rapidly providing cost-effective solutions anywhere in the world present a daunting challenge every company will face.

David Haynes
Sales & Marketing Director
Surface Technology Systems plc

In 2007, we see explosive growth levels in the advanced packaging market. I think there will be substantial growth for the deep reactive ion etch (DRIE) MEMS technology in the advanced packaging market. This increase in demand will be driven by the manufacturing of CMOS sensors and flash memory devices for use in applications such as cell phones and personal media players. This market will be twice its current size by 2010 for MEMS DRIE equipment.

We continue to see positive growth in the MEMS community. Expect to see growth in the initial or more "traditional" MEMS markets, such as inkjet heads, but also in acoustic MEMS applications and the optical MEMS markets.

Jerry Cutini
President & CEO
Aviza Technology Inc.

In 2007, we are seeing different buying patterns among the various segments of IC production. The memory market segment continues to expand in anticipation of the Microsoft "Vista" Operating System in the PC market and the increased memory requirements of modern consumer electronics. Memory manufacturers continue to have a large impact on capital spending, and we believe that trend will continue throughout 2007. However, a slight increase in inventories is generally affecting capacity expansion plans of some IDMs and foundry companies. We expect this situation to correct itself during the course of the year.

Another topic that has been gaining industry attention is the transition to 450 mm wafer sizes. This discussion is still premature based on multiple financial analyses. We believe it will be some time before the industry transitions to 450 mm wafers.

On the technology front, atomic layer deposition (ALD) is "the next critical technology" to enable continued IC device scaling by precisely depositing one atomic layer at a time on the wafer. This state-of-the-art technology is currently in production at 90 nm and below geometries by worldwide DRAM manufacturers, which validates the production-worthiness of this critical technology.

Mary G. Puma
Chairman & CEO
Axcelis Technologies Inc.

After a relatively dormant 2006, semiconductor equipment companies can expect much of the same steady climate in 2007. For implant, 2008 could be a breakout year. Four industry trends will continue to develop in 2007:

• 45 nm will move closer to active production, perhaps in late 2007, while investigation into 32 nm tool development gears up. Companies must continue to develop innovations that offer convincing productivity and yield advantages.
• Process integration will become increasingly important, with customers looking to equipment companies to address many challenges. Equipment manufacturers will be called on to collaborate with customers to solve process integration challenges, both upstream and downstream.
• 300 mm Prime will emerge as a bridge to still-far-off 450 mm, significantly improving fab productivity with new automation features and smaller batches that reduce cycle times.
• Asia — particularly China — will expand its semiconductor dominance.

Bernold Richerzhagen
CEO
Synova SA

2006 was a solid year for the industry, and the outlook for 2007 is positive, as well. A priority will be continuing to explore new end-use application markets for existing technology. From a geographical perspective, China is still growing at an unprecedented rate, and additional production capacity will be required as the country shifts some of its focus from exporting product to addressing the consumer needs of a growing middle class with money to spend. Eastern Europe, with its low-cost economy and highly qualified, well-educated work force, is also a prime candidate for increased private investment, the vast majority of which currently goes into China, India and Southeast Asia.

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