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Opto-WLP for CMOS Imaging Sensors

Optical wafer-level packaging (WLP) technology combines traditional wafer-level techniques with expertise in glass compositions and optical technology.

Philip Garrou, IEEE Fellow, President IEEE CPMT Society, Program Consultant, RTI International, Research Triangle Park, N.C. -- Semiconductor International, 12/1/2006

At the heart of the still-expanding digital camera market is the image sensor — a silicon semiconductor designed to capture photons and convert them into electrons. Charge-coupled device (CCD) technology, discovered at Bell Labs (Murray Hill, N.J.) in the late 1960s, controlled the imaging market for many years. Today, the latest CMOS sensors are continuing to displace the older CCD technology, as their output now rivals that of the quality of the CCD while offering a lower cost and requiring less energy to operate.

Since CMOS design can incorporate image processing and analog-to-digital conversion on the chip, digital cameras have become less expensive to build. In addition, CMOS cameras do not require as many boards and as much circuitry to operate. Today, there are many manufacturers making CMOS image sensors, such as Micron (who acquired Photobit; Boise, Idaho), OmniVision (Sunnyvale, Calif.), STMicroelectronics (who acquired VLSI Vision; Crolles, France), Mitsubishi (Cypress, Calif.) and Kodak (Rochester, N.Y.).

Beyond the digital still camera, these image sensor devices have spread out into other markets, such as PC cameras, toys and games, camera phones, automobiles, security and surveillance, biometrics, medical instruments, and personal digital assistants.

Packaging has been known to add as much as 30% to the cost of the imaging sensor. Image sensors were first assembled in ceramic packages with a glass cover, such as the Amkor VisionPak, which was a ceramic leadless chip carrier. This solution is relatively expensive and takes up significant space in the camera itself. In today’s market, image sensor camera modules are offered as a complete manufacturing solution that integrates an image sensor die with a DSP, optics, passive components and flex-attach circuit. All of the major packaging houses, such as ASE (Taipei, Taiwan), SPIL (Taichung, Taiwan), Amkor (Chandler, Ariz.) and STATS ChipPAC (Singapore), offer such modular solutions. A generic schematic of such a chip-on-board module is shown in Figure 1.1

1. Image sensor camera modules integrate an image sensor die with a DSP, optics, passive components and a flex-attach circuit.

Because CMOS sensors are optical by nature, care is necessary to minimize contamination at every step. Once devices are coated and packaged, any trapped debris will be forever evident in flawed (dark) pixels. Ideally, all manufacturing steps from silicon wafer processes to packaging would occur in the same cleanroom to minimize exposure and handling. This would also eliminate the need for the typical passivation layer between the silicon and optical layers, which can steal up to 20% of the light.

Over the past several years, Schott (Mainz, Germany), in conjunction with Fraunhofer-IZM (Berlin), has been developing a wafer-level packaging (WLP) technology by combining traditional wafer-level techniques with its in-house expertise in glass compositions and optical technology.2,3 The concept of WLP evolved in the 1990s as the small-size, low-weight, low-cost package of merit.4,5

Although these packages save size and weight, CMOS imaging sensor manufacturers were not quick to adopt this technology because mainstream WLPs fabricate the interconnect structure (solder balls) over the surface of the silicon devices and mount the diced WLP die on the PCB face down, whereas CMOS sensing chips must mount face up. An obvious solution is to have the active area of the sensor face up and the area array contacts for the interconnect on the backside of the device. Shellcase (Jerusalem, Israel), recently purchased by Tessera (San Jose), was the first to propose such a technology with its optoelectronic chip-scale packaging (CSP) technology.6

In late 2005, Schott moved its opto-WLP technology to Singapore, and is currently in production with a planned capacity ramp to >7000 wafer/mo by late 2006. A typical Schott opto-WLP process sequence (Fig. 2 ) includes six steps:

2. A typical Schott opto-WLP process sequence.

  1. The devices are first covered with a 500 µm cover sheet of polished Borofloat 33 glass, which has a coefficient of thermal expansion (CTE) that matches silicon’s. The cover glass is bonded using an acrylic polymer adhesive or, for a totally hermetic structure alternative, Schott glass technology.7
  2. The wafer is thinned to ~100 µm, which enables low-profile packaged parts.
  3. Via holes and dicing streets are plasma etched simultaneously through a resist mask. Vias, cut down to the backside of the peripheral pads on the devices, are etched with 70° sidewalls to enable subsequent lithography and sputter coating.
  4. 3. Insulator and metal redistribution traces are deposited and contacted to the backside of the pads through the via openings.
    A plasma-enhanced chemical vapor deposition (PECVD) silicon oxide layer (or a Schott Novolay layer) is deposited in the vias streets at temperatures <180°C for insulation. A second plasma etch step, through photoresist, selectively removes the insulator from the bottom of the vias/streets until the backside of the pad metallurgy is exposed. Insulator and metal redistribution traces are then deposited and contacted to the backside of the pads through the via openings (Fig. 3 ). Benzocyclobutene or other polymeric insulators are used in conjunction with copper or aluminum for this redistribution. If a completely hermetic package is desired, one of the layers of polymer dielectric can be replaced by a layer of glass deposited by Novolay technology.5
  5. Lead-free solder balls are screen printed or placed on the nickel underbump metallization of the solder pads.
  6. The die are singulated through the previously exposed dicing street.

The structure is shown in a cross-section in Figure 4. Figure 5 shows an imaging sensor packaged using this opto-WLP process sequence.

4. A cross-section of a typical opto-WLP.

Offering fully sealed devices for module integration, yield losses caused by particles on the image sensors can be reduced significantly using this package. Beyond this, the company is providing an integration platform for future miniaturization of optical modules by offering the possibility to integrate optical functions like IR filter coatings and lenses at the wafer level. Commercial quantities of the opto-WLP technology are reportedly now available.

5. An imaging sensor package using the Schott opto-WLP.


Author Information
Philip Garrou received his B.S. in chemistry from North Carolina State University and his Ph.D. in chemistry from Indiana University. He is an IEEE and IMAPS Fellow, and has recently served as president of the IEEE Components, Packaging and Manufacturing Technology Society (CPMT , 2003-2005). Garrou currently consults in the area of thin-film microelectronic materials and applications. He was most recently director of technology and director of new business development in Dow Chemical’s Advanced Electronic Materials business.

References
  1. C. Scanlan and N. Karim, "System-in-Package Technology Applications and Trends,” Proc. SMTA Conf. Polymers and Adhesives, 2001.
  2. J. Leib and M. Toepper, “New Wafer Level Packaging Technology Using Silicon-Via-Contacts for Optical and Other Sensor Applications,” 54th Elec. Comp. Tech. Conf., 2004, p. 843.
  3. J. Leib, D. Mund and M. Toepper, “Novel Hermetic Wafer Level Packaging Technology Using Low Temperature Passivation,” 55th Elec. Comp. Tech. Conf., 2005, p. 562.
  4. P. Garrou, “Wafer-Level Packaging Has Arrived ,” Semiconductor International, October 2000, Vol. 23, No. 10, p. 119.
  5. M. Toepper and P. Garrou, “The Wafer-Level Packaging Evolution ,” Semiconductor International, October 2004, Vol. 27, No. 10, p. SP-13.
  6. P Garrou, “Wafer Level Chip Scale Packaging: An Overview,” IEEE Trans. Advanced Packaging, 2000, Vol. 23, p. 198.
  7. D. Mund and J. Leib, “Novel Microstructuring Technology for Glass on Silicon and Glass Substrates,” 54th Elec. Comp. Tech. Conf., 2004, p. 939.
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