3-D Integration Could Improve Yields

When implementing a new technology, one of the first things that comes to mind is possible yield fallout from new failure mechanisms. But during a recent keynote presentation, Susan Vitkavage, project manager of 3-D integration at Sematech, surprised the audience by saying that 3-D integration could potentially lead to yield improvements. The reason is that wafer-to-wafer bonding could add an additional degree of freedom in terms of repairability of memory circuits. Since the main application for 3-D ICs today is memory stacking, the idea of possibly tweaking the yield prior to packaging is very appealing. “That additional n+1 degree of freedom is very attractive, and memory designers are looking into this application,” she said.

3-D integration is a disruptive technology that bridges the wafer and packaging worlds. 3-D enables reduced interconnect delay, form factor and power consumption while allowing heterogeneous integration of numerous devices.

Vitkavage gave the keynote address at Semiconductor International’s Interconnect Workshop, which directly followed this year’s Advanced Metallization Conf. (AMC) in San Diego in October. “The motivation for Sematech to launch a 3-D program had to do with the red brick wall that copper and low-k interconnects hit around 2010, when materials solutions to the RC problem draw to a close. While the industry will buy itself some time using clever solutions, there are fundamental problems going forward,” she said.

One of Sematech’s first goals is cost modeling. To model the manufacture of a particular part, a number of assumptions have to be made about the source material (substrate), mounting orientation, whether die-to-wafer or wafer-to-wafer mounting makes sense, how the electrical bond will be formed, whether through-silicon vias will be used, etc. (Fig. 1). “Die-to-wafer bonding raises the yield because of known good die, but with small die on a 300 mm wafer, this approach could be cost-prohibitive because you could be picking and placing forever,” Vitkavage said.

1. Depending on the complexity and cost target of the device, a variety of process decisions need to be made. (Source: S. Vitkavage)

Ultimately, process flow will be dictated by the end product. She gave the example of a low-cost, low-power part using metal bonding, assuming the last metal level was designed to form the bond layer (raised copper pads). The donor wafer was scribed and thinned to singulate with a dice-before-grind process. Through-silicon vias were optional. The donor die was flipped and bonded to the bottom wafer; bond pads were opened in the periphery. Die-attach time and known good die (KGD) yield were varied. Key assumptions include factory capacity, defined process flow, throughput (wph) and capital cost, material usage per step, scheduled and unscheduled maintenance, personnel required, cost of space, and yield. Not surprisingly, the wafer-level cost increases dramatically for long die-attach time (high-accuracy alignment or slow bond formation) and a higher number of die per wafer (smaller die or higher yielding part).

At the recent SEMICON West show, Sematech gathered packaging experts, device manufacturers, and materials and tool suppliers and conducted a survey of the level of effort needed in the areas of tool development, metrology, prototyping capabilities, thermal modeling, etc. (Fig. 2). Sixty percent of industry participants believe that significant or critical effort was needed in 11 out of the 12 categories. In other words, there is much work to be done.

2. Sematech survey results showed that all areas of development but one require >50% significant or critical level of effort, indicating the enormous amount of work ahead in 3-D integration. (Source: S. Vitkavage)

Sematech’s cost modeling to date has come to the conclusion that wafer-to-wafer bonding generally lowers the overall yield. The yield advantage of a smaller die area is more than overcome by bonding bad die to good die. One can potentially simplify process flows. But the potential for improved repairability through 3-D interconnects has not yet been established or quantified.

Find more information on yield management.