Low-Cost Innovations Abound at IMAPS

Several trends in semiconductor packaging were evident at this year's IMAPS. The common thread is the use of low-cost innovations, which is consistent with the goals of technology roadmaps like the International Technology Roadmap for Semiconductors (ITRS) and iNEMI.

Packaging of RF and wireless devices is more challenging. Frequencies have increased and sizes have decreased to the point that the dimensions of a packaged device are comparable, if not larger, than the wavelength associated with the signal frequency. Shielding and resonance management are very important in this regime.

Researchers from The Citadel (Charleston, S.C.) and GeoMat Insights (Santa Rosa, Calif.) discussed the elimination of bypass capacitors by controlling resonances. Having large, closely spaced power and ground planes in the board or package is not new, but putting a ring of resistive material around the edges of the planes is. The resistive material is added to dampen any electromagnetic wave for which the parallel plane structure would be resonant. If this is enough to make bypass capacitors unnecessary, then board assembly can be much simpler.

Researchers from Bridgewave Communications (Santa Clara, Calif.) and Kulicke and Soffa (Ft. Washington, Pa.) presented work on making coaxial wire bonds. After wire bonding is performed, a dielectric is deposited, coating the bond wires and everything else inside the package. After lithographic patterning, a metal is deposited to create the outer conductor coating for the wires, and connect those sheaths with ground connections in the package and on the die. They have demonstrated the ability to handle frequencies up to 100 GHz.

For high-pincount ICs and systems-in-a-package (SiPs), wiring density of the substrate is limited by the core of the substrate. Plated through-holes in the core are usually spaced on a coarser pitch than the microvias in the buildup layers, which can determine the size of the substrate. Sometimes microvia stacks are not allowed over the through-holes, forcing the need to use more room. Using a coreless substrate can relieve these restrictions.

Work at Cisco Systems (San Jose) on coreless organic substrates shows promise. Not only is the interconnection density improved, but warpage during solder reflow and underfill steps was also kept under control. For flip-chip attach steps, the warpage of the substrate was moderate, but in the die area the coplanarity was within specifications.

Researchers at Samsung Electro-Mechanics (Suwon, Korea) experimented with thin core substrates. Though thick cores can provide the stiffness needed to minimize overlay errors during substrate buildup, they can also be a source of warpage because of the coefficient of thermal expansion (CTE) mismatch with the die. A thin core made of a higher glass transition temperature material was used, because its CTE was a little lower and closer to that of silicon. A land coplanarity improvement of ~30% was reported.

Researchers at Fujitsu (Kawasaki, Japan) reported successful work on thin core and coreless substrates, mainly focused on reducing thermal resistance. A stiffening ring helped with thermal conductance and in controlling warpage for board attachment.

As packages get smaller and more dense, cleaning steps become more important, and it is important that they be low in cost and aggressive at removing impurities, while leaving dielectrics and organic materials unharmed.

Researchers with Air Products (Allentown, Pa.) have developed a low-cost method for removing oxides from metal surfaces using electron attachment. Low-energy electrons (<10 eV) are emitted into a mixture of hydrogen and nitrogen, which are captured by the hydrogen molecules to form atomic hydrogen anions, which then reduce the oxides. There is no need for a vacuum, as with plasma processes, which promises to make this a low-cost process. Success was demonstrated at temperatures as low as 100°C, which promises to make the process compatible with dielectrics and organics.

Hyperflo (Gilbert, Ariz.) researchers and the University of Rhode Island presented work on a non-damaging, submicron cleaning process that uses a concept similar to one used in megasonic cleaning. Vacuum cavitational streaming uses pressure modulation in a vacuum chamber to create and cavitate bubbles in a cleaning fluid. The fluid is introduced when the pressure is low so that it will go into tight spaces. The pressure is then reduced to form bubbles, which are most likely to form on edges and impurity sites. Increasing the pressure causes the bubbles to collapse, and the microstreaming that results delivers the needed force to remove an impurity. Success has been achieved in removing flux residue from porous surfaces, and in cleaning residues from microvias.

In this small sample of papers, it is evident that the assembly and packaging sector of the industry is responding to the calls to both innovate and keep costs down.

Find more information on semiconductor packaging.