Memory Technology: Where Is It Going?

Today, several technologies compete for a market segment that grows faster than the entire semiconductor market: the market of non-volatile memories (NVMs), driven by the rapidly growing demand for mobile storage. Flash memory, costing far less than earlier technologies such as electrically erasable programmable ROM (EEPROM), is currently the overwhelmingly dominant NVM technology. Besides its economic advantage, it offers high-density, fast-reading access and is electrically erasable.

In 2000, the cellular phone that implemented NOR flash technology for code and applications storage was responsible for a first boom. We are now witnessing the second flash boom in which NAND flash plays a major role. NAND flash enables new applications that require even larger densities, such as digital and video cameras, MP3 players, USB flash drives, memory sticks and all kinds of flash card products. NAND is definitely taking the lead in the memory density race by providing multi-gigabit chips already in mass production today. And it seems that this will continue for at least the rest of the decade.

However, with a scaling pace as fast as 2×/year, the conventional floating-gate concept used in flash memory will soon run into fundamental barriers. Numerous alternative memory concepts are looming on the horizon to get a piece of the fast-growing market. Nevertheless, the much larger sales of flash memory support a larger R&D effort to realize next-generation flash technologies. Innovative solutions, such as multilevel programming, the introduction of high-k materials and the introduction of charge-trapping layers, will probably further extend the flash roadmap. They hold the promise to continue Moore's Law toward the 32 and 22 nm nodes. Simultaneously, alternative NVM concepts — either evolutionary or revolutionary — are being explored to eventually satisfy the need for continuously higher storage capacity and system performance, lower power consumption, smaller form factor, lower system costs and long data-retention capability.

1. NOR flash (top) allows fast, random read access, while the NAND configuration (bottom) allows for smaller cell sizes.

NAND and NOR flash: scaling issues

NOR-type flash is the concept of choice for robust code storage (Fig. 1, top). Its architecture allows fast, random read access at the expense of a more complicated technology. Programming is done in ~10 µsec by channel hot-electron injection through a relatively thick tunnel oxide (~10 nm), while the slow (~0.5 sec) erase operation uses Fowler-Nordheim tunneling from the floating gate toward the channel. Typical operating voltages are comprised between ±8 V. The cell size is typically ~10 F², where F is the feature size of the technology. The NAND configuration (Fig. 1 , bottom) allows for smaller cell sizes (~4 F²) because its array configuration includes a minimum number of contacts. Moreover, because the cell is programmed by Fowler-Nordheim tunneling in both directions (write and erase), the channel length can be scaled more aggressively than in the NOR case. Drawbacks of this configuration are the higher voltages (up to 18 V), thinner tunnel oxide (~7.5 nm), long programming time (~300 µsec) and the slow random read access time (~1 µsec). NAND, being denser and cheaper, is the technology of choice for high-density data-storage applications.

From a scaling point of view, the tunnel oxide and, hence, the program/erase voltages, are the major obstacles. Especially for the NAND configuration, the tunnel oxide cannot be further thinned without compromising reliability. One way to circumvent this problem is to introduce high-k materials in the tunnel layer as well as in the interpoly dielectric layer. Recently, we obtained very good results with HfAlO as an interpoly dielectric. With its relatively high k value and low-leakage currents, this material is found most promising in the fast-evolving flash arena.

Further scaling is obtained by using multilevel schemes, which enable the storage of two bits in one physical cell by programming to four different levels. However, when scaling the technology to <45 nm, electrostatic interference between adjacent cells starts to occur, which is particularly worrisome for the multilevel case. This problem can be addressed by switching to charge-trapping concepts based on nitride (or other trapping layers).

It should finally be noticed that, for embedded NVM solutions, different choices are to be made because the memory footprint is, to a large extent, determined by the periphery (because of the high program/erase voltages) and the integration cost, not simply by the cell size. Additionally, embedded flash technology is tailored to the specific needs of the application, typically leading to different cell types and process flows. An example is the split-gate structure (Fig. 2 ) that was developed specifically for embedded applications. Programming is done by the high-efficiency source-side injection mechanism, while erase can be performed by tunneling toward a junction or, alternatively, the top gate.

2. With a split-gate structure, programming is done by the high- efficiency source-side injection mechanism, while erase can be per formed by tunneling toward a junction or, alternatively, the top gate.

Charge trapping: the obvious competitor

As the scaling of the conventional floating-gate cell becomes ever more complicated, opportunities for other concepts are emerging. Today, the most obvious alternative is definitely charge trapping in nanocrystal- and nitride-based layers. These structures (Fig. 3) do not suffer from electrostatic interference issues. Simultaneously, the high sensitivity of the conventional floating-gate cell with respect to local tunnel oxide defects — the main limitation for further scaling of this layer — is circumvented by spreading the charges in the trapping medium. For nanocrystal layers, when insufficient nanocrystals are present, charges that have been injected can get trapped in between the crystals. This can cause an upward shift of the threshold voltage window. However, increasing the density of nanocrystals enhances the risk for percolation from one storage node to another, hence compromising the main advantage of a local charge-trapping memory. Alternatively, nitride layers are known to have a sufficiently large density of traps without showing these percolation problems (Fig. 3 ).

3. The most obvious alternative to the conventional floating-gate cell is charge trapping in nanocrystal- and nitride-based layers.

Nitride-based memories have recently regained a lot of attention with the advent of the dual-bit nitride cell, usually referred to as NROM. This memory concept, storing two bits at opposite sides of the channel, offers a viable alternative for the multilevel floating-gate technology in terms of cost and achievable densities. But from a scaling perspective, the possible interference of both bits will prevent aggressive channel-length scaling. This limitation is very fundamental and will compromise the cell size and read-out current already in the near future (sub-100 nm). Moreover, the simultaneous presence of electrons and holes in the nitride layer causes many reliability issues, such as limited retention after cycling, that are not easily solved in large memory arrays.

The most scalable device today seems to be the conventional SONOS cell, which is programmed and erased by tunneling to and from a nitride storage layer. We are currently investigating an innovative SONOS cell concept that combines a high-k top dielectric layer and a multilevel programming scheme. The goal of these investigations is to develop a cell that has similar endurance as the conventional SONOS, but with superior retention capabilities and higher drive current. This concept could pave the way toward the 32 and 22 nm nodes, and maybe even below.

Emerging non-volatile memory technologies

A number of alternative memory technologies based on a variety of different concepts and materials have been actively investigated in the last decade and, in most recent years, their numbers have dramatically increased.

Initially, the technologies mainly targeted improved performance for embedded memory applications, potentially replacing EEPROM and embedded flash. Replacement of all embedded memories, including SRAM and DRAM caches, by a new “universal memory” (UM) technology was even envisaged. The first widely investigated memory technology in this respect is the FeRAM. In FeRAM, data is stored as the direction of the polarization in a ferroelectric capacitor, which can be switched by an electric field. The low-voltage, low-power and fast-write characteristics, combined with good reliability (e.g., endurance >10¹² cycles), make this an ideal memory technology for portable systems and smartcards; FeRAM specifications come closest toward that of UM. However, apart from large integration process complexities related to the ferroelectric and electrode materials, the major issue of FeRAM is poor scalability because its signal is based on capacitor charge that scales down with each technology node, resulting in a loss of sensitivity. The fabrication of a 3-D capacitor could solve that issue, but its process complexity seems prohibitive. As a result, the technology is not scalable beyond 100 nm. Current existing products and continuing development (up to 64 Mb in 130 nm technology, featuring a cell size of 15 F²) show the viability of FeRAM for a number of niche markets, but its clear lack of scalability excludes it from becoming a mainstream (embedded) NVM technology.

MRAM is a second alternative technology that is pursued mainly because of its ultrafast switching potential combined with virtually unlimited cycling. Moreover, as the concept is based on the variable magnetoresistance of a magnetic junction device and not on charge, signal should not be a scaling barrier. MRAM was therefore considered an excellent UM technology beyond the 100 nm node. However, MRAM is found to suffer from a number of issues (i.e., half-select disturb and high-programming current [several mAs] needed to generate the switching magnetic field). Moreover, the switching field does not scale with feature size. These issues seriously impact the minimal cell size (reportedly ~30-40 F² for technologies to 130 nm). New developments such as spin-torque-transfer-switching (switching by pushing a current through the tunnel junction device) may solve the main MRAM issues, but still need to be proven. Until then, embedded MRAM may find niche applications where non-volatility has to be combined with SRAM-like fast nanosecond switching.

These examples clarify that simple process technology as well as cell scalability are stringent requirements (even more than excellent operation characteristics) for any NVM technology to become mainstream — not only for standalone (where cell size is of main importance because of the huge memory density required), but also for embedded memory (has to be compatible with fast-scaling standard CMOS processes). The more recently investigated PCRAM technology was found to obey both characteristics (i.e., relatively easy process compatibility as well as excellent scalability).

PCRAM is a resistor-based memory, where the resistor is made of chalcogenide material that, by means of Joule heating, can be either molten and successively quenched in a high-resistive amorphous phase, or heated below the melting point to induce crystallization in the low-resistive crystalline phase (Fig. 4 ). The current to induce the heating up to the melting point is still relatively large (typical 0.5 mA) but, contrary to MRAM, is shown to scale down with cell size. While operation characteristics such as speed and endurance do not match UM requirements, they are still superior to that of flash memory. Cell sizes of 10 F2 or smaller are shown to be possible, making this technology a serious competitor for NOR flash. Further cell size scaling is projected beyond the 25 nm node, where serious limitations for both NOR and NAND cell scaling are expected. This, in combination with the potential of PCRAM for multilevel operation, may even make PCRAM a competitor for NAND flash technology. The strong interest in PCRAM makes it the most advanced of all alternative memory technologies now in development (512 Mb in 90 nm technology has already been reported).

4. PCRAM is a resistor-based memory, where the resistor is made of chalcogenide material that, by means of Joule heating, can be either molten and successively quenched in a high-resistive amorphous phase, or heated below the melting point to induce crystallization in the low-resistive crystalline phase.

The growing importance and need of NVM, as well as the limited performance and anticipated scaling issue of the now standard flash technologies, will continue to feed the development of new memory concepts and materials. A focus in recent years has been on material systems that enable RRAM, where this switching is established by an electric field. Some of the investigated material systems show the promise to combine the main features of PCRAM (easy integration and excellent scalability) with improved characteristics (faster switching with lower currents). While a myriad of different material systems (including even organic and molecular material systems) are proposed, the most prominent candidate technologies (Fig. 5 ) are conductive-bridging RAM (CBRAM), based on a programmable metallization cell (PMC), and conductive switching in binary oxides, called oxide RRAM (OxRRAM). Most of these concepts are still in early development, however, and physical mechanisms need to be further clarified to validate scalability prospects. Moreover, reliability and integration technology need to be demonstrated.

5. The growing importance and need of NVM, as well as the limited performance and anticipated scaling issue of the now standard flash technologies, will continue to feed developments of new memory concepts and materials.

Conclusion

The ever-growing need for data storage in modern, mobile multimedia applications drives the tremendous effort in the development and scaling of NVM technology. Today, flash is the mainstream NVM technology, and will continue to be down to the 45 nm node. Currently, several ways are being investigated to overcome its main scaling issue. The introduction of both high-k materials and charge-trapping layers offer good prospects to push the flash roadmap toward the 32 and 22 nm technology nodes. Meanwhile, a variety of alternative memory technologies have been or are being actively investigated, both for standalone and embedded memory applications. To become mainstream, these technologies must obey the stringent requirements of process compatibility and good scalability. In addition, they have to compete with the progress made in flash technology development, which still gets the majority of R&D. Therefore, some of them, such as FeRAM, end up in niche applications rather than taking over.

The resistor-based PCRAM is the most advanced alternative memory concept in development, and might eventually become a competitor for both NOR and NAND flash. Novel RRAM concepts might even extend the capability of PCRAM with improved characteristics. However, these technologies are still in their infancy, and further research is required to validate their integration, scalability and reliability capabilities.