DFM Takes on Process Variability

Through a variety of products, some specific to the chemical mechanical planarization (CMP) process, others to lithography, EDA suppliers have begun addressing process variability. A new development specifically accounts for transistor variability, using TCAD to provide insight into the fundamental physical phenomena that ultimately impact device performance and yield. Synopsys (Mountain View, Calif.) is introducing a so-called process-aware design for manufacturing (PA-DFM), designed to analyze variability effects at the custom/analog design stage for 45 nm devices.

The PA-DFM tools, Seismos and Paramos, address two major sources of variability in a design: proximity variations caused by stress and other neighborhood effects, and global variations due to the spread of manufacturing process parameters across different die and wafers. The products were created to complement the company's recently released suite of yield analysis tools, PrimeYield, and statistical timing analysis and extraction tools, PrimeTime VX and Star-RCXT VX.

“These tools will enable designers to see how much they can push the design rules and realize the full potential of technology scaling,” said Terry Ma, director of product marketing for Synopsys' TCAD group. “One of the pain points designers face at 45 nm and below is process variability as new process steps, such as strain engineering, are added for advanced technology nodes. These stress proximity effects can significantly impact transistor variations. Unlike litho-based (OPC/RET) DFM, however, there are no knobs to turn to for compensation of layout dependency due to stress effects in strained silicon. Designers need tools to evaluate the impact of variations and make appropriate changes to the design to guarantee parametric yield.”

Seismos shows the effects that a different proximity will have on transistors with the same dimensions, looking at the stress and other process-related proximity effects on the layout.

Paramos links the process parameters, including the distribution, to SPICE parameters so the user can perform a detailed analysis of global variations at the circuit level. “The important thing is that we work off the layout and the GDSII, which the designers are familiar with,” said Ma. By using accurate physical models of the manufacturing process, custom designers can account for manufacturing variability without major changes to the current physical design flow. The Figure shows the many parameters involved in the model.

The interplay of processes, parameters and performance metrics that are managed in a process-aware design for manufacturing (DFM) environment. (Source: Synopsys)

“The challenge is also providing a DFM solution that is incremental and can plug into the customer's existing DFM flow,” said Ma. Seismos is also capable of performing interactive “what if” analyses to optimize design layouts.

The PrimeYield suite of tools is designed to accurately predict design-induced mechanisms that threaten manufacturing tolerances by providing automated correction guidance to upstream design tools. Built on production baseline technology and manufacturing models used by leading foundries and IDMs, PrimeYield is designed to correct manufacturing sensitive design patterns before tapeout.

The program has individual modules to address lithography errors, CMP variation and particle-induced defects. A lithography compliance checking (LCC) module identifies lithographic errors, model-based CMP locates and analyzes uneven metal fill, and critical area analysis enables (CAA) identification of areas of high yield loss in the layout.

Back in August, Synopsys completed its acquisition of Sigma-C AG, a Munich-based EDA tool supplier. With this, it acquired the company's Solid+ tool that analyzes variability within the lithography process on the cell level. Together with Solid E, this approach uses a shared central database of lithography models to help ensure accuracy and consistency of simulation results between design and manufacturing.

The Solid+ tool uses advanced simulation methods to identify and analyze lithography problems such as “hot spots” early in the design process. Its enhanced algorithms allow rapid simulation of large areas of a layout on the cell level with no compromise of accuracy.

Find more information on yield management.