Double Patterning Takes Hold as Bridge Technology

Though no more than a year ago the mere mention of double patterning sent shudders through the semiconductor manufacturing community, this year has seen a great deal of positive talk about the technique. Not that it doesn't still make chipmakers tremble, worried about what it will mean in lost productivity or overlay errors, but people seem to have come to terms with the fact that a bridge technology is needed to move the industry from immersion to extreme ultraviolet (EUV) lithography.

Double patterning techniques were much talked about at the Photomask Technology conference, held in September in Monterey, Calif. “This year, I think for the first time we're seeing the true application of a design solution to a major manufacturing problem — in this case a lithography problem. And that is tight pitch,” said Franklin Kalk, chief technology officer at Toppan Photomasks (Round Rock, Texas), in an interview at the conference. “I think because people have not in the past really been able to see a bridge to 32 half-pitch, in this case I think finally we're seeing that, and everyone's really excited about it.”

This year's keynote address was presented by Martin van den Brink, executive vice president of marketing and technology at ASML (Veldhoven, Netherlands), who asserted that double patterning is now the only way to go to bridge the gap at 32 nm, before EUV is ready.

Water-based 193 nm immersion lithography is widely accepted as the technology of choice for getting to the 45 nm half-pitch and perhaps beyond. But the technique is not sufficient for reaching 32 nm. To do that would require pushing the numerical aperture (NA) past 1.35, the theoretical limit of water-based systems. Although research groups are putting a great deal of work into exploring high-index immersion fluids, resists and lens materials that would enable higher NAs, van den Brink puts little stock in the viability of the economic model involved.

The key, then, for bridging the gap between immersion lithography and EUV is to find ways of lowering the k₁ factor, which is already a difficult challenge for lithographers, but surely cannot go below 0.25 with current methods. Van den Brink presented double-exposure lithography — whether dual trench (negative) or dual line (positive) — as the only realistic means of getting below a k₁ of 0.25.

ASML has done some proof-of-concept work recently with Cadence Design Systems (San Jose) and IMEC (Leuven, Belgium) to demonstrate the feasibility of using double patterning to reach an effective k₁ below 0.20. In one example, the researchers printed flash memory patterns at a 32 nm half-pitch with a positive double patterning technique. Using ASML's 1700i immersion scanner with an NA of 1.2 and Cadence's Virtuoso Image Decomposition tool, the researchers were able to print the lines with a final k₁ of 0.19. The Figure demonstrates the results, with the first patterning in the light color laid down next to the second patterning in the dark color.

1. Researchers used double patterning with water-based immersion lithography to achieve a proof-of-concept 32 nm flash memory pattern. The final k1 was 0.19 after the split. (Source: ASML/Cadence/IMEC)

Although various presentations from the team also showed results of 32 nm logic double patterning, van den Brink pointed out that flash is more easily achievable with double patterning. Flash is a 1-D scaling problem, and logic is a 2-D problem, he said, and double patterning works better for 1-D structures. The increasing difficulty of pattern stitching goes from flash to DRAM to random logic, he said.

Besides potential difficulties with block stitching, double patterning creates additional steps and challenges in design and maskmaking and in the wafer fab, and requires an extension to the infrastructure, noted Bob Naber, product marketing director for RET solutions and DFM at Cadence. There is also concern about overlay, which needs to be incredibly tight and could lead to changes in critical dimension (CD).

In a recent interview at IMEC's annual research review meeting, Luc van den Hove, IMEC's vice president of silicon process and device technology, explained the research organization's plan for extending lithography. “The third option in our program is indeed double patterning, where we plan to use water-based immersion lithography and combine that with double exposure,” he said. “In this way, in principle, we can increase the resolution by a factor of 2.”

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