New Structures and Materials Help Flash Shrink

It seems flash memory is everywhere. Digital music players and digital cameras depend on it. Cell phones and PDAs are more capable because of it. As Lehman Brothers (New York) Managing Director Edward White pointed out at September's SEMI New England Breakfast Forum, demand for flash memory appears to be highly elastic. As the price drops, new applications become possible and demand increases. Like the transistor itself, inexpensive non-volatile memory appears to have nearly unlimited market potential.

Yet, like the transistor, the success of flash memory is at least partly due to continuous improvement. Manufacturers face unrelenting pressure to increase memory density by cutting costs. Market leader Samsung (Seoul, Korea) has stated that it will double flash capacity every twelve months, a rate even faster than proposed by Moore's Law. Unfortunately, shrinking flash memory cells becomes more difficult with each new technology generation.

A NAND flash cell includes two transistor gates. The control gate reads and writes charges to the floating gate, which is electrically isolated and charged by quantum tunneling through a surrounding oxide layer. Writing data to flash is relatively slow compared with dynamic memories such as DRAM or SRAM. Moreover, flash wears out and is therefore not suitable for “working” memory, requiring frequent write and erase cycles.

Because of their dual gate structure, flash cells are also relatively large. As density increases, capacitive coupling between adjacent floating gates can affect the threshold voltage of the cells. At the same time, the number of electrons actually stored in the floating gate decreases. By the 30 nm node, according to Samsung's Kinam Kim, the gate will contain <100 electrons, and the loss of just 10 electrons will be enough to cause data loss.¹

Manufacturers are turning to a variety of new designs in order to meet scaling requirements. Samsung is developing two of these: charge trap flash and phase change memory.

Charge trap flash is a relatively straightforward extension of existing memory technology. Instead of a floating polysilicon gate, it depends on a SONOS (semiconductor-oxide-nitride-oxide-semiconductor) capacitor structure. Charge is injected into the structure, as in NAND flash, but is stored in trap sites in the nitride layer. The oxide “sandwich” prevents data loss and reduces coupling relative to floating gate designs. However, high erase voltages allow electrons to tunnel back into the nitride layer from the gate, preventing complete erasure. Lower erase voltages reduce back tunneling, but also increase the time needed. This problem might be alleviated, according to Sanghun Jeon and coworkers at Samsung's Advanced Institute of Technology, by using a high dielectric constant material, such as Al₂O₃, for the blocking dielectric. Using a high-k material reduces back tunneling by allowing designers to use a thicker layer to achieve the desired capacitance.² In September, Samsung announced that it had created a 32 Gb NAND flash cell using TANOS (tantalum-alumina-nitride-oxide-semiconductor) charge trap structures. Fabricated with 40 nm process technologies, the charge trap cells are less than one-fifth the size of conventional NAND cells.

The second alternative, phase-change memory, is far more radical. It uses controlled heating to switch a chalcogenide glass between amorphous and crystalline states. The two states have different electrical resistance, which the circuit uses to determine whether a 1 or 0 is stored (Figure ). A common chalcogenide glasses, germanium-antimony-tellurium (GST), is used in CD and DVD media. The blank media is first initialized to the crystalline state, then selectively melted by the write laser. The melted spots solidify in the amorphous phase, which is less reflective than the crystalline phase. The read laser sees these dark spots, encoding the desired bit stream.

This drawing shows an integration scheme for the phase-change memory cell. It uses controlled heating to switch a chalcogenide glass between amorphous and crystalline states.

Also in September, Samsung unveiled a prototype 512 Mb memory, dubbed the PRAM, based on GST. No other alternative to flash has yet achieved such high density. Though ferroelectric memories (FeRAM) and magnetoresistive memories (MRAM) are now in production, both are limited to 4 Mb chips.

Proponents of PRAM note that it offers shorter write times and unlimited write cycles, making it a potential universal memory, suitable for both non-volatile and dynamic storage. A prototype is not a commercial product, and large scale adoption of PRAM probably remains several years away. Still, the Samsung announcement suggests that memory proliferation will continue, unimpeded by technological barriers.