FinFETs Demonstrated for Analog and RF Applications
Aaron Hand, Managing Editor -- Semiconductor International, 11/1/2006
Although advanced finFETs have proved to be complicated transistor structures, companies and research organizations have been forging ahead to make them viable production-worthy devices. IMEC (Leuven, Belgium) is one of the latest organizations to demonstrate the finFET's potential — producing the first operational RF circuits and operational amplifiers using finFETs with a 45 nm physical gate length and a metal/high-k gate stack.
IMEC researchers designed, processed and successfully tested both a two-stage operational amplifier with 50 dB gain and a 2-8 GHz tunable oscillator. FinFETs offer better circuit performance than planar bulk CMOS for relatively low-frequency applications (<5 GHz) that demand a high gain. However, speed still needs to improve for applications at higher frequencies.
Unlike bulk devices, whose intrinsic gain drops at 45 nm, finFETs have higher intrinsic amplification because of a better control of the short-channel effects. This makes finFET structures more suited to high-gain operational amplifiers.
On the other hand, current finFET technology has a maximum cut-off frequency of only 100 GHz — almost 3× lower than with planar bulk CMOS. This is caused by the series resistance of the fins and the lower mobility at the sidewalls of the fins. Because of this, finFETs are showing good performance characteristics for devices up to 5 GHz, with even better performance at lower frequencies compared with planar transistors.
“Scaling beyond 45 nm demands significant changes in process modules such as gate materials and/or device structures,” said Luc Van den Hove, vice president of silicon process and device technology at IMEC. “An early assessment of the potential of the different options for their analog/RF performance is needed to maintain a competitive position. Therefore, this research forms an important aspect within our sub-45 nm CMOS research.”
Future work at IMEC will focus on increasing the speed of finFETs by increasing mobility and decreasing the relatively large series resistances and the extrinsic capacitance between gate and drain.
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