It's Not the End of Copper/Low-k

I don't often start off this page with a limerick — okay, this is a first — but here's one courtesy of Susan Vitkavage, manager of 3-D integration at Sematech :
 
Your product will determine the way
That 3-D is built today
The lowest cost flow
Is the best way to go.
It's not the end of copper/low-k!

This is a light-hearted comment on what is actually a very serious effort at Sematech and within the industry to evaluate the potential of 3-D integration and apply some cost and yield modeling to the surprisingly wide variety of possible approaches.

But the last line, “It's not the end of copper/low-k!”, hits home in that I believe there's a general perception in the industry that everything that can be done has been done in the back-end-of-line (BEOL). Copper resistivity has pretty much been optimized, and there are no other solutions after copper. To get lower k values, it will be necessary to go to a porous material, which creates difficult integration issues such as moisture absorption. This is why low-k requirements have been getting pushed out in the International Technology Roadmap for Semiconductors (ITRS) since 2000, not standing at around k=2.4. That's pretty far from where everyone wanted to be. As Sematech's Greg Smith noted in a VLSI Multilevel Interconnection Conference (VMIC) paper, “If the industry had succeeded in following the 2000 ITRS, we would now be integrating dielectrics with a bulk constant of 1.3 and a k_eff of 1.9!”

It seems that the front-end-of-line (FEOL) is getting all the attention. Technologies such as strained silicon metal gates, high-k gate dielectrics, advanced transistor structures (i.e., finFETs), silicon on insulator (SOI), hybrid-orientation technology (it's HOT!) and the like are where the excitement is, where the most advancements can be made, and where the greatest hope lies in the never-ending quest to higher functionality and speed and lower power.

It's certainly true that all these FEOL areas are getting a lot of attention and deservedly so (irrational exuberance? Probably not). But it would be a mistake to think that BEOL technology advancements have been ground to a halt.

I can tell you that BEOL technology is alive, having over the past two months attended the VMIC and the Advanced Metallization Conference (AMC). We also hosted a workshop after AMC, and presented a webcast on material challenges for copper/low-k in September (see also “Copper/Low-k Challenges for 45 and 32 nm”).

The focus is mostly on trying to be clever about managing integration issues, which are typically trade-offs between added capacitance (i.e., raising the effective k) and trying to optimize manufacturability and minimize reliability problems, such as electromigration, stress voiding and time-dependent dielectric breakdown (TDDB). Most, if not all, of these trade-offs become more difficult to manage as the industry pushes to lower-k dielectrics, which are invariably weaker. They also get more challenging with scaling, as Laura Peters notes in this month's feature, “Achieving Superior Interconnect Reliability at 65 nm and Beyond .”

There's significant basic research going on as well. While it's true that it will prove difficult to further reduce or even maintain copper resistivity, it could be possible with thinner barrier layers deposited by atomic layer deposition (ALD). The industry is also (finally) making progress with porous dielectrics. IBM, for example, plans to implement porous SiCOH (k=2.4) for the 45 and 32 nm device generations.

Research also continues into ways to seal porous materials or remove the porogens after chemical mechanical planarization (CMP, in work underway at Sematech). Air gaps are being considered as a way to extend the use of existing material sets, and there's certainly great potential in 3-D integration and even LC or optical interconnection layers above the chip. We'll likely see all of these come into play in the future, depending on the application. In the meantime, there's still plenty of life in copper/low-k.