Wafer-Level 3-D Integration Moving Forward
3-D integration can alleviate interconnect delay problems, while reducing chip area. Three options are described, based on whether the ICs have been designed for 3-D interconnection.
Philip Garrou, IEEE Fellow, President IEEE CPMT Society, Program Consultant, RTI International, Research Triangle Park, N.C. -- Semiconductor International, 10/1/2006
Three-dimensional integration represents a system-level integration scheme wherein multiple layers of planar devices are stacked and interconnected using through-silicon vias in the Z direction.¹
Conceptually, 3-D can alleviate interconnect delay problems, while reducing chip area. If a large number of the long interconnects needed in two-dimensional structures can be replaced by a short vertical interconnect, this would greatly enhance the performance of logic circuits. For instance, logic gates on a critical path can be placed very close to each other by positioning them on multiple active layers. Circuits with different voltage requirements and/or performance requirements can also be put on different layers.
3-D wafer stacking is achieved by the production of full wafers of a specific function (i.e., embedded processors, DSPs, SRAM, DRAM, embedded wireless networks, etc.). These wafers or singulated known good die (KGD) are then vertically interconnected to create a functional device. The 3-D concept thus allows the integration of otherwise incompatible technologies, and offers significant advantages in performance, functionality and form factor. Technologies that could be conceivably included in such a 3-D stack include antenna, sensors, power management, and power storage devices. Having shorter signal paths between die make it possible to improve the system's performance by allowing for the system to run faster; it also wastes less power. Wire length is a major concern when it comes to power usage, and keeping wire lengths short goes a long way toward keeping power use down. Much of the concern about using such 3-D, stacked-die solutions is about heat removal, but the use of through-hole vias reduces the overall wire length, which actually somewhat reduces heat generation.
Presentations at the recent Electronic Component Technology Conference (ECTC) offered some insight to the progress being made in 3-D wafer-level integration. In a panel discussion, advances being made on the 3-D front for wafer-to-wafer (W2W) and die-to-wafer (D2W) interconnection were summarized.² It is becoming clear to many that the initial concept of W2W bonding is being supplanted by D2W bonding because of D2W's ability to:
- assemble only KGD
- easier alignment tolerances
- ability to interconnect die of dissimilar sizes
- ability to interconnect die from dissimilar size wafers for “heterogeneous integration”
Three realistic options appear available for through-via formation depending on whether the ICs have or have not been designed for 3-D interconnection (Fig. 1 ).
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| 1. Through-via formation can be done in one of three ways, depending on whether the ICs have been designed for 3-D interconnection. |
Designed for 3-D with FEOL through-vias
If the chips are being designed for 3-D implementation, through-vias may be front-end-of-line (FEOL) fabricated by any facility currently practicing DRAM or embedded DRAM deep-trench capacitor technology. For 3-D, 2-4 µm diameter vias are currently typical and could be getting smaller. This is the route chosen by startup Tezzaron (Singapore) with their “Super Contact” technology.³ Since the through-vias are created in the wafer when the IC interconnect is fabbed, there is no need to leave exclusion zones where on-chip interconnect cannot be routed. Such wafers can be subsequently thinned down to expose the back of such through-vias (typically tungsten, although copper is possible), and routing and backside pads created to allow interconnect to other die/wafers.
Designed for 3-D with BEOL through-vias
If back-end-of-line (BEOL) processing is chosen for the through-vias, exclusion zones must be left during design and fabrication of the IC. The 3-D foundry/packaging house can subsequently etch the through-vias before mounting on a handle wafer and thinning (vias first) or after attachment to the second die/wafer (vias last). Japanese startup ZyCube (Tokyo) is a proponent of the BEOL vias first technology4; IBM research has been a proponent of the BEOL vias last technology.5
Not designed for 3-D with BEOL through-vias
If the chips/wafers already exist and cannot be redesigned, the Association of Super Advanced Electronic Technologies (ASET, Tokyo) technique6 of redistribution of the vias to the area between the peripheral pads and dicing street is required. Such processing can be done by a packaging or MEMS foundry with Bosch etching capability. One could conceive of putting the insulated through-vias right through the peripheral pads; however, recent placement of support pillars under the pads to better resist cracking during wire bonding of fragile low-k interlayer dielectric (ILD) based chips sometimes precludes this option.
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| 2. In a typical CCD sensor, imaging pixels are connected laterally with various components by inter-chip interconnects. In the 3-D VISA design, the chips are connected vertically with through-wafer. |
At the same meeting, Christopher Bower of Research Triangle Institute (RTI) described recent advances in the DARPA VISA (vertically interconnected sensor arrays) program.7 The D2W 3-D integration technology under development by RTI International and DRS Infrared Technologies (Dallas) uses a BEOL vias-last technology.
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| 3. A vertically interconnected two-layer IC stack is shown. |
The VISA process flow starts with IC wafers designed with through-via exclusion zones, fabricated in a standard CMOS foundry. A metal redistribution layer is deposited and patterned on the IC1 wafer. The IC2 wafer is then mounted on a handle wafer (face down) and thinned using backgrinding and chemical mechanical polishing (CMP) processes. While still mounted on the handle wafer, the thin IC2 wafer is singulated, and the individual KGD are bonded to known good sites on the IC1 wafer.
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| 4. This infrared thermal image was obtained from a vertically interconnected 256 × 256 pixel VISA structure. |
Figure 3 shows a cross-sectional SEM micrograph of a stack consisting of two IC layers fabricated using the process described above. The micrograph was obtained following the completion of the vertical interconnect fabrication sequence, but before the patterning and passivation of the top metal. The top IC layer (IC2) is about 30 µm thick, composed of ~10 µm of SiO2 IC ILD and 20 µm of silicon, with a thin backside passivation layer. The IC2 layer was bonded to the underlying IC1 using a high-precision die bonder with split-prism optics and a polymer adhesive. Post-bond alignment accuracy between the two IC layers is typically >2 µm. The separate IC layers are interconnected by means of high-aspect-ratio (~8:1) copper vertical interconnects 4 µm in diameter. The vertical interconnects are insulated from the bulk silicon with a conformal dielectric layer. Figure 4 shows an infrared thermal image obtained from a vertically interconnected 256 × 256 pixel VISA structure.
| Author Information |
| Philip Garrou received his B.S. in chemistry from North Carolina State University and his Ph.D. in chemistry from Indiana University. He is an IEEE and IMAPS Fellow, and has recently served as President of the IEEE Components, Packaging and Manufacturing Technology Society (CPMT , 2003-2005). Garrou currently consults in the area of thin film microelectronic materials and applications. He was most recently director of technology and director of new business development in Dow Chemical's Advanced Electronic Materials business. |
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