Reliability Fundamentals at 45 nm

Laura Peters, Senior Editor -- Semiconductor International, 10/1/2006

Scaling to 45 nm and beyond has the unfortunate effect of pushing CMOS materials closer to their intrinsic reliability limits. At the 65 nm node, gate oxide thickness is ~1.2 nm, with a leakage of ~100 A/cm² at 1.0 V. Scaling further, issues of high current densities, voltage overshoots, localized hot spots on the chip and high thermal resistance packaging become concerns, as explained by a recent presentation by Joe McPherson, senior fellow of Texas Instruments (Dallas) at the Design Automation Conference in San Francisco. McPherson addressed the impact of scaling on gate leakage, negative bias temperature instability (NBTI), RC delay, electromigration, stress migration and Joule heating. Though in most cases there is a trend toward degraded reliability with continued scaling, the industry is finding remedies so that device reliability specifications can be met.

Strained silicon is one process enhancement that provides up to a 40% increase in transistor drive current (I_on) without a significant increase in leakage current (I_off). Though scaling of the gate dielectric is limited to ~1.2 nm, in cases where high gate leakages can be tolerated, nitrogen can be added to the oxide to achieve reasonable physical thickness and acceptable defect density. In cases where high leakages are not tolerated (portable applications), high-k dielectrics will eventually be needed.

NBTI is known to cause a shift in the p-channel threshold voltage and a decrease in mobility of the inversion channel in pMOSFETs. Si-H bonds, which are needed for interface-state passivation, become broken under use conditions. NBTI has become more important today because electric fields in the gate oxide are higher, devices operate at higher temperatures and voltage headroom (V_g-V_t) is smaller than it was in past technology nodes. NBTI is most evident at low voltages and significantly impacts minimum voltage operation.

Hot carrier injection from the channel to gate oxide can be reduced by lightly doped drain implants and voltage reduction. However, when minimal voltage levels are reached, HCI becomes an increasing concern. Scaling also has a negative impact on the electrostatic discharge robustness of CMOS devices (Table 1 ).

The move from cobalt silicides to nickel silicides for low resistance contact to the S/Ds and gates resulted in lower resistivity and less consumption of silicon. As shown in Table 2 , the move to certain alternative silicides that consume less silicon than nickel unfortunately does not buy the industry resistivity advantages.

While the implementation of interlevel dielectrics with lower k values serves to reduce the interconnect RC time constant, low-k dielectrics tend to lead to degraded electromigration (EM) because of the material’s lower modulus and lower thermal conductivity than SiO₂. Copper EM generally occurs along the copper/capping layer interface. For the same current density, EM performance is expected to degrade with scaling because of the relative increase in copper-interface area vs. volume. Ensuring EM robustness will eventually drive new processes (ALD barriers) and layers (CoWP caps).

With scaling, stress migration (SM), which results in small voids in vias, becomes more common because fewer vacancies are required to cause an unacceptable rise in via resistance. Typically, SM has been most prevalent where single, medium-sized vias are connected to wide copper lines, but recently they have been reported for narrow metal leads as well. If implemented, CoWP copper caps may help SM as well as EM issues.

For low-k ILDs at the 65 nm node, nominal minimum metal widths are ~100 nm, with similar spacing. Given process variations, the spacing can be 70-80 nm. In CVD low-k films, the Si-O network bonds are replaced by terminated Si-CH₃ bonds. This leads to reduced electrical breakdown strength (E_bd) and time-dependent dielectric breakdown (TDDB), which both decrease as k decreases.

Beyond mechanical and electrical strength, the impact of Joule heating becomes more significant with low-k films due to the poorer thermal conductivity. The temperature rise is most severe at the upper levels of metal.

Killer defects are generally regarded as being half the width of the metal space, or 16 nm at the 32 nm node. McPherson showed that, even on a process where no physical defects were detected, an increase in the time spent between copper CMP clean and the capping layer deposition from 1 hr to 3 hr to 7 hr each led to decreases in the low-k dielectric breakdown strength.

Clearly, an acceleration of reliability learning will be needed to offset these negative trends in nearly every aspect of device reliability as the industry continues to scale critical dimensions.