A Preview of New Technologies at IEDM

Peter Singer, Editor-in-Chief -- Semiconductor International, 10/1/2006

The 52nd Annual International Electron Devices Meeting (IEDM) will be held Dec. 11-13, 2006, at the San Francisco Hilton. The conference encompasses radically new devices, such as a nuclear-powered sensor that can run for decades without refueling, chips for DNA synthesis, magnetic biochips and, not surprisingly, a wide array of breakthroughs in the field of nanotechnology.

Most of the conference, however, is focused on recent advances in mainstream CMOS and memory technology. Here's a preview of some of the highlights, as provided by conference organizers:

Best pFET performance — TSMC (Hsinchu, Taiwan) researchers studied the effect of multiple stressors on CMOS devices on (110) and (100) substrates. They also considered the effects of different channel directions. Among other results, they saw an 87% improvement in drive current for compressively strained pFETs with SiGe source/drain contacts on a (110) substrate with a <111> current flow orientation. Record pFET performance was demonstrated — I_on=900 µA/µm at I_off=100 nA/µm and V_dd=1.0 V at 40 nm gate lengths. Since the current CMOS wafer orientation standard is a (110) surface with <110> current flow, these findings may lead to changes in standard CMOS processing.

High-performance 45 nm process — Toshiba (Tokyo) researchers will report on a complete high-performance bulk silicon technology for the 45 nm technology generation of logic devices. It marks the first appearance of ultrahigh-numeric aperture (NA) immersion lithography (NA=1.07) in a bulk logic process, and integrates it with many advanced device-building techniques. These include embedded DRAM, multiple silicon stressors (embedded SiGe, stress memorization, and dual-stress liners), a hybrid dual-damascene structure with a porous low-k dielectric (k=2.7), and a change in the way source/drain diffusion and extension is performed. The technology was used to build a very dense SRAM (0.248 µm²) with high drive currents for both nFET and pFET transistors.

High-performance, low-power CMOS — Sony (Tokyo) researchers built high-performance, low-power CMOS devices incorporating an array of advanced technologies: high-k dielectrics with metal gates, strained silicon with SiGe source/drains and (110) wafer surface orientation. The metal gates were built using a low-temperature dummy-gate process to minimize damage to the dielectric. High drive currents of 1050 µA/µm (nFET) and 830 µA/µm (pFET) were achieved, at low gate leakage currents of 0.03 A/cm² and below.

Two low-power 45 nm processes — Two noteworthy papers describe low-power 45 nm processes. Crolles2 Alliance (Crolles, France) researchers will present a cost-effective 45 nm technology platform for wireless multimedia and consumer electronics applications, where power consumption is a major concern. The goal was process simplicity and no added mask steps going from an existing 65 nm CMOS technology. They used a 45° rotated wafer with a (100) surface orientation, which enabled mask-free strain engineering (tensile strain stabilized by an anneal). The process also incorporates immersion lithography (NA<1) and an advanced interconnect — up to nine layers of copper and a low-k dielectric (k~2.5). They built low-power transistors operating at 1.1 V, with drive currents of up to 660 µA/µm, and SRAM cells as small as 0.25 µm2.

Meanwhile, Freescale (Austin, Texas) researchers will describe a different low-cost 45 nm process. The key is a single metal gate, which is combined with a high-k gate dielectric. It demonstrated a record NMOS drive current of 1550 µA/µm. The process is a modified silicon on insulator (SOI) 65 nm technology that incorporates dual etch-stop layer stressors, a hafnium-based gate dielectric fabricated via atomic layer deposition (ALD), and a sputtered tantalum carbide gate electrode.

Phase-change memory — Researchers from a joint project between IBM (White Plains, N.Y.), Qimonda (Munich, Germany) and Macronix (Hsinchu, Taiwan) will describe a memory cell using a promising phase-change material, doped germanium antimonide (GeSb). It required a reset current of <100 µA and showed rapid change between states, good data retention and cycle life, and relative temperature insensitivity. The device (Figure ) consists of a 20-200 nm-wide bridge of GeSb connecting two underlying electrodes. The bridge width is defined lithographically, but its height is defined by the GeSb layer's thickness, thus enabling designers to use ALD as well as lithographic techniques to scale the device. The researchers said that with a 3 nm-high bridge, the memory device could scale to a cross-sectional area of just 60 nm².

This phase-change memory consists of a 3 nm-high bridge of GeSb connecting two underlying electrodes. The bridge width is defined lithographically, but its height is defined by the GeSb layer’s thickness, thus enabling designers to use ALD and lithographic techniques to scale the device.

Find more information on wafer processing.