Thermal Processing Takes on New Materials, Lower Temps

Of all the thermal oxides used in device manufacturing that must be precisely grown, doubtless the most critical of all these is gate oxide formation, which has become increasingly thinner from process node to process node. Over the years, gate oxide has gone from a thickness of ~250 Å in the late 1980s to 10 or fewer atomic layers, depending on the application.
 
Unlikely to slacken, this evolution will continue to require considerable R&D expenditures by device makers and equipment suppliers alike.

Change, change everywhere

There are many thermal processing trends. In the thermal annealing arena, it is not front-page news that the gradual migration from batch thermal annealing to single-wafer rapid thermal processing (RTP) continues. It began in logic ~12 years ago, when RTP began being used for junction annealing in addition to the silicides that had been its first applications.

“Logic has traditionally been the entry point for RTP developments, and DRAM has followed closely behind by a node or two,” said Gary Miner, CTO for the Front-End Products Group at Applied Materials (San Jose). “Now this is happening with flash memory also. As NAND flash scaling is driving shorter thermal budgets, memory market applications for RTP are expanding.”

Another trend is a broadening of temperature range requirements for RTP. High- and low-end temperature steps are emerging. The low temperatures are primarily driven by the transition to nickel silicide. As technology moves to new nodes and thermal budgets fade, it is not atypical to run <300°C in RTP. Five years ago, there was little capability to measure and control in that range.

The Vantage RadOx RTP system advances device scaling by supporting critical oxidation steps in low thermal budgets. (Source: Applied Materials)

From a deposition perspective, atomic layer deposition (ALD) has arrived. Its first use was with DRAM storage dielectric, using Al₂O₃. Those films are now changing and other materials are being introduced, such as hafnium and aluminum combinations. Although there were predictions about other steps going to ALD, such as the barrier seed layer for interconnect, in most cases, physical vapor deposition (PVD) still prevails.

Some new material introduction seems the result of a need without a clear solution. Certainly in the gate stack area, engineers maintain a search for materials with the right dielectric and metal properties to enable the correct work functions, proper turn-on voltages for transistors, and that fit into a standard process flow. This has been more challenging than anticipated, and still no clear path exists. However, in terms of deposition methods, matters have stabilized. Certainly, ALD capability and functionality are important, as are extensions of PVD capabilities in electrodes. As Miner indicated, precision thermal and thin-film control has been able to meet requirements, even if the materials themselves are different.

At 65 nm, there are no major thermal processing hurdles or capability gaps. Some materials — such as in the broader use of nickel silicide deposited by PVD — required thermal annealing changes. “From the gate perspective, gate oxide scaling was achieved and adopted for logic and DRAM, where an oxide can be formed, nitrogen added using plasma nitridation, some post annealing done, and the polysilicon capped, all within one tool,” Miner said.

The high-k promise

Prevailing wisdom indicates 45 nm will be attained through evolutionary — not revolutionary — developments. Capability extensions have been formulated for these technologies to reach that node, including gate dielectric. High-k for gate has been under consideration for years — it would come at 90, then 65, now 45 nm. Actual production will tell the story but, increasingly, companies are dropping high-k from their 45 nm roadmaps. If it is used at all, it will be for a few niche applications. Instead, continued scaling and improvements of the gate oxide can be attained through advanced processes; stable, proven oxynitride continues to improve.

The great conundrum is 32 nm. Strain engineering work using selective SiGe, stressed nitride films, and shallow trench isolation (STI) has demonstrated substantial performance improvements without physical scaling. It appears that 32 nm performance requirements can be reached with strained engineering on planar devices, without resorting to more complex 3-D structures such as finFETs.

Transitions are also occurring in oxidation. Gate oxidation was the first to go from furnace to RTP. There has also been a swing in other critical oxides, particularly in logic and flash. In the latter, this has been driven by radical oxidation, which creates oxygen radicals using a purely thermal scheme, not plasma. These radicals improve STI liner corner rounding, round the control gate during sidewall oxidation, and boost the reliability of tunnel and inter-poly dielectric oxides.

Furnaces pull their weight

Regardless of developments, the prediction of the demise of the furnace is unfulfilled. According to Tanja Claasen, product manager, vertical furnaces at ASM International (Bilthoven, Netherlands), the low cost of ownership (CoO) of furnaces is a powerful drive, and investments in the technology continue. Clearly, new materials are a challenge for furnaces but, as she stated, new materials like hafnium, zirconium, ruthenium and others are being run in furnaces. “The question is which to select and how to do the necessary costly characterization and development,” she explained. “For instance, of 10 precursors developed, only one may eventually be used in the production environment.”

Thermal furnaces face no serious challenges at 65 nm. At 45 nm, there will be some thermal hurdles besides materials. One of these will be defect control, which will require single-digit numbers for small particles. Albert Hasper, general manager at ASM Europe, thinks furnaces have an advantage. “ALD single-wafer processes with reduced cycle times have a problem,” he said. “An isothermal reactor has no spots of uneven temperature, giving it an inherent advantage. Also, ALD’s on-and-off mechanics are simplified by doing wafers in a batch instead of individually. The furnace’s simpler design and chamber environment increase reliability and simplify meeting 45 nm node contamination and process control requirements.”

May Su, vice president and general manager of the Thermal Business Unit at Aviza Technology (Scotts Valley, Calif.), views CoO and productivity as the road to success in the batch environment. “This is why DRAMs have kept this process for so long,” she said. “Existing capabilities continue being extended; for example, in the lower-temperature silicon nitride oxidation area.”

Another application being focused on is radically assisted oxidation for things such as STI liners and gate and tunnel oxide, where the device manufacturer wants lower leakages. Crystal-insensitive oxidation seems to work well here. As manufacturers pursue sharp junctions, work continues to attain lower thermal budgets. Beyond 45 nm, aside from new materials, most of the focus is on stress and strain engineering.

Focusing on annealing

For logic, the issue is ultrashallow junctions for extension implants. This seems to drive most annealing implant conditions. The aggressive junction scaling that device makers are implementing is a result of the halt in transistor scaling from a dimensional standpoint and the lack of a good high-k gate material.

“Implant energies must drop to produce these ultrashallow junctions, and the commensurate anneals are shifting from spike anneal to flash anneal to maybe something else,” said Ivan (Skip) Berry, director of technologies at Axcelis Technologies (Beverly, Mass.). This brings up several issues. One is that, at the 65 nm node, boron implants for p-type junctions have a projected range of ~5 nm, with most of the dopant within 10 nm of the surface. At 45 and 32 nm scales, conditions are reached where all the implant resides in the few top atoms.

Rework is another issue. If the lithography is badly done, for example, wafers must be reworked. When rework becomes another variable, it raises the specter of whether it is possible to obtain consistent resistivity and dopant profiles after annealing. In a typical rework, the wafer goes through an APM clean that removes silicon and dopant. These are issues with implant RTP and clean. Multi-sidewalls are another. Some manufacturers use two or three different spacers to tailor the junction profile. This raises concerns over sidewall material compatibility with the boron, arsenic, or phosphorous outdiffusion.

1. Hot wall systems can potentially avoid emissivity dependence at 45 nm and below. Shown here is a new annealing technique concept, based on a wafer floating on a gas bearing, which uses conductive heating to minimize emissivity effects. Sub-second spike anneals can be attained by the conductive heating mechanism at <300°C. Unknown as yet is whether such a system could do flash annealing. (Source: ASM International)

A fact coming into play is emissivity across the wafer leading to associated local temperature non-uniformity — pattern effect. The question is whether there are workarounds to it, or if a different annealing technology is needed to get around pattern effects. An annealing technique independent of wafer emissivity would be ideal; unfortunately, it does not yet exist. Hot wall annealers are less sensitive to emissivity than lamp annealers, and show promise for pattern effect reduction. However, the question is whether hot wall can meet the need for a very short spike or flash annealing.

Flash annealing has across-wafer uniformity issues — either with laser stitching or emissivity — that come into play. Solid-phase epitaxy is viewed as a solution, but such approaches tend to have end-of-range damage effects that increase leakage current. According to Berry, cluster ion implant promises to do solid-phase epitaxial regrowth without end-of-range damage. If it works, flash anneals may not be necessary. “It looks promising, particularly for boron implants, but work is needed,” he said. “In current device technology nodes, it’s possible to minimize pattern effects using the hot wall RTP approach.” Whether this will continue to work through 32 nm is undetermined. Much will depend on how fast a ramp-up is necessary. Hot wall reactors cannot do flash anneal like a laser can. Combining a laser and conventional spike anneal may be useful to optimize activation, diffusion and damage removal.

Straining to continue

Progress can continue on its present polysilicon gate path, with extreme shallow junctions and stress engineering, at least through 45 nm. However, stress engineering has issues: how to alter process conditions to affect the retained stress and stressor layers, especially when dealing with both compressive and tensile stressor layers. Layer stress relaxation must be avoided. Anneal can play an important part, as well as exposure to UV light and ionizing radiation.

By far, the biggest problem is consistency run-to-run and lot-to-lot of a 45 nm extension junction. Engineers are struggling to understand the surface effects of dopants that reside in the first five atomic layers, which must be relied on to diffuse in and create the junction. Stressors — whether tensile or compressive — tend to alter diffusion. There are surface chemistry issues when attempting anneals. If hydrogen or oxygen is present at the surface, the activation or diffusion is affected. Surface roughness comes into play, the interface between the silicon and the sidewall spacer is important; how the surface is terminated prior to putting on the spacer can affect ultimate results.

2. ALD lends itself to the formation of stoichiometric films through a self-saturating reaction mechanism. (Source: TEL America)

Some are predicting going as low as 200 eV boron implants for 32 nm. If so, then everything becomes a surface effect, and the surface chemistries taking place or the roles of radicals (oxygen, hydrogen, nitrogen or something else) in these activation processes are still not well understood. Approaches tend to be empirical. Also, implanted surfaces become extremely reactive. The silicon crystal’s chemical bonds have been destroyed by the implanted material, and there are very reactive materials, such as boron, that readily oxidize when cleaning. In a traditional APM clean, a boron implant can increase reactivity by an order of magnitude.

Paul Timans, director of technology for the RTP Products Group at Mattson Technology (Fremont, Calif.), agrees that the overall CMOS scaling picture below 65 nm, from the transistor formation perspective, shows that the traditional approach of scaling gate dielectric thickness is presently stuck. “Since the silicon oxynitride solution persists, there is little room for shrinking, and delays in high-k metal gate adoption don’t help,” added Andrea Toennis, vice president and general manager of Mattson’s Thermal Products Division. Thus, the big hitter in the scaling arena is strain engineering, which has become prevalent, although there are ongoing efforts to improve channel mobility through the pursuit of new crystal orientations, or even new channel materials, but much of this is further down the road.

With limited gate dielectric scaling, there is a significant focus on alternative approaches, especially the control of short-channel effects. An attitude gaining in importance is that anything that can conceivably be done to reduce the polysilicon depletion in the gate dielectric should be done, contributing to its scaling.

Shallow junction formation is another factor for RTP that continues gaining importance. There have been some aggressive proposals in the International Technology Roadmap for Semiconductors (ITRS) about how much junction should be scaled, even leading to a fairly critical need to adopt advanced implant schemes and significantly control diffusion. That opens new technologies in the RTP arena, such as the millisecond anneal, which also plays in the field of controlling polysilicon depletion by getting activation in the gate electrode. Much can be done to improve channel mobility and help drive current on the transistor; however, these parasitic resistances in the contact regions and the junctions ultimately severely limit performance. So the focus is on good electrical activation in doping profiles, which ties back to the shallow junction topics, and also on novel contacts, nickel silicide and so on, essential now.

For 45 nm, different options are being considered, and even more so for 32 nm. The most likely path seems to be to continue pushing bulk silicon — although in some cases the silicon on insulator (SOI) structure has been adopted — and to continue strain engineering work. All of this will mean increased process and temperature control.

According to Anthony Dip, product manager for the Thermal Processing Systems Group at TEL America (Austin, Texas), given the aspect ratios, memory makers are looking to higher-k materials and possibly going exclusively to ALD for these films.

Front-end thermal budgets are practically becoming non-existent. Thermal processing equipment suppliers must provide processes that stretch the technology. Chemistry is becoming the big enabler — precursors that make things occur thermally at lower temperatures (options such as plasma). The pressure is still for solutions that allow up to, perhaps, a 200°C thermal budget drop, post-gate implants. This is strongly dependent on chemistry. “As equipment manufacturers, it becomes difficult for us to do both — to play with such exotic chemistries in a way that is scalable to a production environment and simultaneously develop the hardware to deal with these chemistries,” Dip said. “Ten years ago, we’d design a machine to do nitride. The chemistry was familiar, the film targets were clear and understood; the process wasn’t easy, but it was engineerable. Today, we’re supposed to design a platform for a chemistry that will not be known for another two years — impossible. In the metals, for example, I’ve had in mind looking into metal CVD, but who knows what the metal system may be in five years; there’s little use in attempting to develop something for that. Many things on the drawing board look good, but are one-generation solutions and users aren’t going to buy into them; they’re not going to tool up for one technology node and then obsolete the hardware.”

A major problem the industry faces is addressing thermal budgets toward the end of the transistor manufacturing process, with the materials challenge close behind. These come in different forms. One is stress engineering. Users want films with programmable, engineerable stresses. Some of that is chemical-based, some of it is deposition.

It appears everything is being reduced to heat and chemistry.