NEC Announces SiP Technology

Flip-chip-on-chip is a popular option for applications requiring two die, logic and memory, with high interconnection density between them. When the memory die is larger than the logic die, however, this is problematic. NEC Electronics (Kanagawa, Japan) and NEC (Tokyo) recently announced an interconnection technology to address this case called “SMAFTI,” which was also featured in a paper at this year's Electronic Components and Technology Conference (ECTC).

The main targets for this packaging technology are applications that require high-speed access to large amounts of memory, such as cell phones and graphic processing systems.

Though flip-chip-on-chip would provide the high-speed interconnection, making connections to external I/O pads is a problem if the memory die is larger. Typically, the external I/O pads are on the logic die. Putting them on the memory die would mean making a simple memory/logic mix on the memory die, eliminating some of the advantages of making them separately. Keeping logic and memory on separate die allows the manufacturing process for each to be optimized at minimum cost, which is one of the basic philosophies of system-in-package (SiP) design.

1. The SMAFTI process flow primarily uses wafer-level steps. (Source: NECEL)

After this interposer is fabricated on the handle wafer, the memory die are flip-chip attached onto it and underfilled. After the underfill is cured, the memory die are then overmolded and cured. The handle wafer is then removed, leaving a “wafer” of memory die embedded in molding compound, with the SMAFTI interposer as the face. Logic die are then flip-chip attached to this “wafer” and underfilled. The solder balls for external connection are simply placed on the I/O pads and reflowed. A dicing saw is used to separate the devices.

For the prototype in the paper, large memory die (7.35 × 12.7 mm), each with 400 electroplated bumps, were thinned to 500 µm prior to attachment. The logic die were 5.31 mm2, and were thinned to 100 µm prior to attachment.

The details of the lead-free via metallization are shown in Figure 2 . The total face-to-face distance between the die is ~60 µm. High-temperature storage tests were performed at 150°C for up to 1000 hours, which indicated that the joints were metallurgically stable and reliable.

Thermal cycling tests showed, and finite element analysis confirmed, that the underfill material must be optimized to give acceptable results. For the two materials examined in the paper, one yielded all failures after 500 cycles, while the other material yielded all passes.

2. Most of the metallization scheme uses wafer-level steps, and the balls are just tin-silver solder. (Source: NECEL)

Many of the process steps are at the wafer level. Even the flip-chip and underfill steps are of the flip-chip-on-wafer variety. No details were given about how the handle wafer is removed.

This packaging process has many steps, which raises the question of its cost. If high speed and high density were not needed, then a less expensive process would probably work well. However, compared with other processes that provide high-speed and high-density interconnect between the logic and memory die, the complexity and cost of this process is comparable. Through-silicon via technologies might serve the same purposes, but they are more suited to situations where the die size needs to be limited.¹

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