Minimize Leakage Power and Process Variations With Dynamic V_t Control

Dynamic threshold voltage (V_t) control offers a potential solution to increasing leakage power and yield loss associated with scaling.

Aashish Patel, Transmeta Corp., Santa Clara, Calif. -- Semiconductor International, 10/1/2006

Semiconductor designers are facing numerous challenges as they migrate their existing designs or start new designs in 90, 65 nm and finer process geometries. Two of the biggest challenges are the increasing power specifications because of leakage power and potential yield loss caused by increasing process variations. Though there are some solutions that assist with lowering leakage power or managing process variations, none of the solutions provides an effective solution to both issues. Dynamic threshold voltage (V_t) can be a solution to both challenges; however, in order to understand the effectiveness of dynamic V_t control and other potential solutions requires knowledge of various power states and their respective components in design. Most designs have two primary power states: active state and standby state.

Active power

A device in the active state is operating at some frequency and working on a given set of tasks. Power in the active state, or active power, is a combination of dynamic (switching) power and leakage power.

P_active=P_dynamic+P_leakage

The frequency and supply voltage of the device influences the dynamic power component of active power. The leakage power component is strongly influenced by the supply voltage, temperature and V_t. In 130 nm and prior semiconductor geometries, dynamic power was the major contributor to active power, while leakage power was a minor contributor. Therefore, in the past, device manufacturers were able to minimize active power consumption by scaling to newer, smaller process geometries. Smaller geometries allowed devices to run at the same frequency but at a lower voltage, which reduced dynamic power consumption.

1. Leakage power increases exponentially as semiconductor devices move to finer geometries.

Unfortunately, leakage power increases exponentially as devices move to finer geometries (Fig. 1 ). In 90, 65 nm and finer geometries, leakage power can be a significant component of active power. In some instances, a 90 nm device consumes less dynamic power than the same device at 130 nm, but the total active power consumption of the device is greater at 90 nm because of leakage power.

Factors contributing to an exponential increase in leakage power include the decreasing dimensions of transistors and the continued scaling of the V_t relative to the supply voltage. The V_t is the voltage at which a transistor is switched on — the higher the V_t, the slower the transistor; the lower the V_t, the faster the transistor. However, with 90, 65 nm and finer geometries, a lower V_t results in an exponential increase in leakage. A substantial increase in leakage power, and therefore also active power, can have many negative effects on system design. Higher leakage power can also affect consumer electronic devices.

Standby power

In addition to increasing power consumption in the active state, leakage power also increases power consumption in the standby state. The standby state, also known as the sleep state, is a lower power state that the device can be placed into when there are no pending tasks. Power in the standby state, or standby power, is mostly a function of leakage power.

The standby power specification of semiconductor devices may significantly increase in 90, 65 nm and finer geometries because of exponentially increasing leakage power. For example, a mobile device with high standby power may result in a lower idle battery life for mobile applications. Moreover, higher standby power specifications can also mean idle plugged-in consumer devices. The idle power consumption of devices and resulting applications can be minimized with dynamic V_t control.

Dynamic V_t control

The use of dynamic V_t control to minimize standby power is easily understood. When a device is in the standby state, dynamically increasing the V_t of the transistors will result in a substantial reduction in leakage power. Even though increasing the V_t will reduce the switching speed of the transistors, the device is in a sleep state, and therefore transistor speed is irrelevant.

The use of dynamic V_t control to minimize active power is not as obvious. As described earlier, active power is a combination of both dynamic and leakage power. At first, it may seem that the obvious solution to minimize active power is to minimize or eliminate leakage power; however, further analysis shows that some leakage power is required to minimize active power. The interaction between the supply voltage, V_t, frequency and other design (logic depth) and process variables results in the active power curve illustrated in Figure 2 .

Figure 2 illustrates dynamic power, leakage power and the active power for a device at a fixed frequency. The active power curve is the dynamic power curve plus the leakage power curve. The X axis represents a balance between the supply voltage and V_t required to maintain the device at a fixed frequency. The manufacture of semiconductor devices is prone to numerous manufacturing process variations (Fig. 3 ), and leads to variations in the V_t of devices of the same design.

Process variations

In order to account for process variations in their designs, foundries provide a “SPICE box” to designers, outlining the fastest and slowest transistor speeds in their process (Fig. 4 ). Since there are two types of transistors in a CMOS process (NMOS and PMOS transistors) foundries provide five different values that form the four different corners and the center of a SPICE box — denoted as fast/fast (FF), slow/slow (SS), fast/slow (FS), slow/fast (SF) and typical/typical (TT). Typically, parts designed for one supply voltage and manufactured in the FF corner will have the highest frequency and provide the best performance, but will also consume the most power. Similarly, parts manufactured in the SS corner will be the slowest, but will consume the least power.

In 130 nm and prior geometries, the amount of variation between the SS and FF corners was not significant. Some semiconductor devices could be designed for the TT point, and designers could expect that all or a vast majority of the parts within the SS to FF process variation space would still meet the desired power and frequency specification. However, with 90, 65 nm and finer geometries, this is no longer true.

With 90, 65 nm and finer geometries, the process variations and resulting distribution of parts have grown substantially. In effect, the “SPICE box” discussed earlier has grown, leading to a wider spread between the FF and SS corner (Fig. 5 ). The wider spread results in a wider distribution of both the frequency and power specification of semiconductor devices; as a result, many parts do not meet the frequency and power design targets. Device manufacturers may have no choice but to attempt to market a much higher power specification for their device or throw away parts that do not meet their specification. Discarding otherwise good parts because they do not meet power or frequency specifications can reduce the effective yield and increase net die cost. However, dynamic V_t control can be used to tune these parts to meet specification. For the parts distribution not meeting the power specification, increasing the V_t will reduce leakage power, resulting in many of the parts meeting the power specification. Similarly, for the parts distribution not meeting the frequency specification, dynamic V_t control can be used to increase the frequency of the affected parts. Figure 6 illustrates two sample yield curves — with and without dynamic V_t control.

Other solutions

A design that employs dynamic V_t control will have a versatile solution for both the increasing leakage power problems and yield loss caused by expanding process variations. However, there are other solutions in the semiconductor industry to help counter leakage and process variation issues. The most popular solutions are:

• Clock gating
• Power domains/voltage islands
• Dynamic voltage and frequency scaling/voltage ID
• Multiple V_t transistors
• Traditional body bias solutions

Clock gating

Clock gating is a popular technique used to reduce active power in a system. Clock gating normally refers to turning on the clocks to specific logic blocks only when there are tasks pending. When there are no tasks pending, the clocks to specific logic blocks can be turned off, reducing the dynamic power portion of active power for a specific block only. However, clock gating only turns off the clocks and not power to logic blocks that are not being used. These logic blocks still dissipate leakage power, which can be substantial in 90, 65 nm and finer geometries.

Furthermore, clock gating cannot compensate for the expanding process variations in 90, 65 nm and finer geometries. That is, with clock gating, a semiconductor designer will still have a wider distribution of power and frequency specifications — some of which may not meet the desired specification.

However, clock gating is complementary to dynamic V_t control, and should be used in any power-sensitive design to minimize dynamic power.

Instead of simply turning on the clocks to logic blocks when required, a better solution would be to turn off power to logic blocks that are not being used.

Power domains/voltage islands

One way to minimize both active and standby power is to either turn off power or reduce the voltage to a logic block when it is not being used. With no supply voltage, the logic block cannot contribute to leakage power. With a lower supply voltage, the logic block will consume far less leakage power than at a higher supply voltage. However, there are several engineering challenges that need to be addressed before power domains can be implemented in a semiconductor design. For example, the design has to be partitioned such that certain logic blocks can be turned off, or designed to operate at a lower voltage when not being used. This introduces several engineering challenges, including proper timing when blocks are turned on and off. Designers may need to level-shift digital signals between voltage supply domains, which can introduce timing issues. A design utilizing multiple power domains will need to conduct a very thorough timing analysis over a range of voltage, temperature and process variations, compounding the timing analysis problem.

Though power domains may help minimize some active power and standby power at the cost of engineering resources and time to market, power domains do not help with the process variation issues described earlier. That is, reducing some power by implementing power domains will lower the power numbers across the entire distribution, but the width of the distribution will stay the same. Power domains only turn off or lower the supply voltage to certain logic blocks; however, active power is both a function of supply voltage and frequency.

A solution pioneered by us to control active power is to dynamically control the supply voltage and frequency of a semiconductor device. For example, when less performance is required, the system can lower the frequency and supply voltage of the device. Since dynamic power is proportional to the frequency and voltage squared, reducing the frequency and voltage can result in a cubic reduction in dynamic power. Even though this method optimizes the active power for a specific workload, for workloads requiring the maximum frequency and therefore the maximum voltage, the power consumption will be the same as a semiconductor device without dynamic voltage and frequency scaling. However, the same system board-level circuits used to enable dynamic voltage scaling can also be used to compensate for some of the process variations seen in 90, 65 nm and finer geometries. For example, if a part is very leaky, it may also be very fast and may consume more power than the desired specification. The supply voltage for this part can be reduced to lower leakage power, but since the part is fast, it may still work at the desired frequency specification. Conversely, on the other side of the distribution, parts that operate slower than the specification can be supplied with a higher supply voltage to increase the frequency. Though the power consumption of the part will increase, it may not exceed the specification. This method is typically referred to as “voltage ID.”

Though having a voltage ID setting will help reduce the distribution between the slowest part and the most power-consuming part, there are limitations to the extent voltage ID can help. Specifically, the minimum voltage required to maintain stability and maximum voltage to maintain reliability limit the range of supply voltages that can be applied. Furthermore, with a voltage ID solution, customers that integrate the device into their systems may have to qualify all the different voltage ID parts independently to ensure the quality of their system board power supply.

Customers would much rather have solutions internal to the semiconductor device with no system board effects. Solutions like dynamic V_t control and multiple V_t transistors are internal to the semiconductor device and typically have no system board effects.

Multiple V_t transistors

Foundries typically provide three V_t process options — high, medium and low V_t. Having only three options forces the designer to either optimize for performance, power, or settle for an intermediate step, sacrificing both power and performance.

However, designers can also use different V_t transistors for different logic blocks and logic gates within a device. That is, designers can use a low V_t, high leakage transistors for the “critical path” where performance is a requirement, and high V_t transistors in parts of the chip where performance is not critical. Though this sounds like a reasonable solution, there are numerous issues that need to be overcome. For example, determining the critical path in a design is a very difficult task requiring numerous engineering resources and expensive specialized timing tools. Furthermore, in many cases, running timing tools on semiconductor designs with all possible parameters and applications is simply prohibitive — both from a schedule and resource perspective.

There are also additional timing issues that need to be addressed. For example, if a design uses dynamic voltage and frequency scaling to control active power, transistors with higher V_t may become critical and limit voltage scalability of the device. Furthermore, multiple V_t transistors have to be manufactured in separate process steps; therefore, the resulting transistors can suffer from mismatch that may cause additional timing issues.

Finally, multiple V_t transistors cannot compensate for process variation issues. Even though the process variations for higher V_t transistors may be lower, the low V_t transistors will have a large variation and, therefore, multiple V_t transistor designs are still susceptible to process variation issues.

Designs utilizing multiple V_t transistors can also use dynamic V_t control to help mitigate process variation issues and further optimize both active and standby power. Retrofitting existing designs with multiple V_t transistors is possible with some engineering effort; however, a traditional body bias-based solution cannot be easily retrofitted.

Traditional body bias

A body bias-based solution, also known as back bias, substrate bias or well bias, provides the same advantages of dynamic V_t control; however, implementing body bias with traditional methods is impractical for general use.

Implementing traditional body bias will require significant engineering resources and time to add metal wiring to connect the bodies of NMOS and PMOS transistors to separate voltage supplies. Significantly changing a design adds additional risk, increasing the probability a design will not work as originally designed. Furthermore, retrofitting an existing semiconductor design to include metal layers to implement body bias is prohibitively expensive and time consuming.

Summary

Compared with the other methods for power reduction discussed, dynamic V_t control may offer the best solution for both the increasing leakage power and the expanding process variations .

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Author Information

Aashish Patel is the director of technical marketing at Transmeta , where he is responsible for all aspects of technical marketing for IP, and engineering services and products. Since joining in 2000, Patel's experience has included management positions in the OEM technical support and the customer applications engineering divisions. Patel graduated with a bachelor's degree in Honors electrical engineering from the University of Waterloo in Canada.

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