Transistor Gate Dielectric Physics, Processes and Characterization Evolve

Oxynitride extends SiO₂'s applications to 45 nm. Nitrogen incorporation is a complex process requiring close control since the interface-trapped charges it induces are essential to gate dielectric integrity.

J. Li, A. Groenendyk, A. Fuerst and R. Carey, Intel Corp., Fab11X, Rio Rancho, N.M. -- Semiconductor International, 10/1/2006

The gate dielectric is a critical component for the CMOS transistor. The evolution of silicon dioxide (SiO₂) has spanned over forty years, and oxynitride is the material that bridges past and future. Gate oxide nitridation is one of today's most critical wafer fabrication operations.

SiO₂ has a long life as a gate dielectric material because of its physical and chemical properties. CMOS technology has required constant evolution and downward thickness scaling to follow Moore's Law, with gate dielectric thickness predicted to go <1.0 nm this year. Since SiO₂'s physical thickness cannot be <1.0 nm, this requirement must be met by a continuous shrink of electrical thickness. One approach is to use SiO_xN_y by nitridizing silicon oxide or depositing oxynitride directly on the silicon substrate. The oxynitride is an extension of SiO₂, primarily because of its higher dielectric constant, lower gate leakage, and higher breakdown field voltage. Oxynitride carries CMOS to the 45 nm node. High-k dielectrics have been studied for a decade as gate dielectric candidates, yet only in the past few years have we seen major progress on high-k dielectric gate applications for beyond the 45 nm node.

SiO₂ as a gate dielectric material

Integrity of the critical gate dielectric plays an important role in transistor switch speed, power consumption efficiency, and device reliability. SiO₂ has been the dielectric of choice for decades because of unique chemical and physical properties and its ease of process and integration. These characteristics include thermodynamic stability, native oxide of silicon, and a stable Si/SiO₂ interface. SiO₂ is also an excellent insulator because of its large 8-9 eV energy bandgap. The large barrier height of 3.1 eV and 4.5 eV for hole and electrons, respectively, keeps carriers in the channel. Electrically stable, silicon has a low trap density at the <100> surface.

With all the benefits it provides, SiO₂ has its own issues for microelectronic applications, primarily reliability concerns caused by electrical charges trapped at the Si/SiO₂ interface and on the SiO₂ surface. Most commonly seen charges are interface-trapped charge (Q_it), fixed charge (Q_f), oxide-trapped charge (Q_ot), and mobile ionic charge (Q_m).

As IC density and device scaling have followed Moore's Law and gate oxide thicknesses have been considerably reduced, the interface is playing an increasingly important role. When thickness reaches ~1.2 nm, the SiO₂ film no longer possesses bulk film properties; instead, interface characteristics become dominant. Here, Q_it becomes the most important charge, with profound impact on device performance.

The origin of the interface charge is the unpaired dangling bond of silicon at the SiO₂/Si interface. One common practice to reduce Q_it is H₂ annealing after gate oxide growth. While this effectively reduces Q_it by passivating the dangling bond, H₂ passivation is a reversible process. Bonded hydrogen atoms can desorb and depassivate the dangling bond.¹ Considerable work has been done toward the understanding and practical application of interface charge passivation. One of the best known is the study of deuterium by Foley² and his colleagues, who compared the desorption rate of deuterium and hydrogen annealed SiO₂, demonstrating that deuterium desorbs at a much lower rate than hydrogen because of stronger bonding to silicon atoms.

Gate oxynitride processes

While device performance demand drives shrinks, gate oxide thickness is close to only a few molecular layers of SiO_w and reaches its physical limit at the 130 nm node. The International Technology Roadmap for Semiconductors (ITRS) states that gate oxide thickness must be <1.0 nm.

Obviously, SiO₂ cannot support the ITRS beyond 2006. The industry responded to the challenge with a two-phase approach. The first was converting conventional SiO₂ to a SiO_xN_y film; the second was to introduce a material with a dielectric constant higher than SiO₂'s. The first phase has been widely used for the 130 to 65 nm nodes. The second is close to implementation for application at 45 nm and beyond.

There is literature that describes numerous ultrathin oxide applications.^3-6 A distinct feature of SiON is that nitrogen incorporation is not a thermodynamic-favored process. At room temperature and atmospheric pressure, there is no stable SiON phase.⁷ The actual nitrogen incorporation can only happen through two mechanisms. One is low energy states in the SiO₂ film and interfaces, generated by crystalline defects such as dislocations, stacking faults, vacancies and dangling bonds. The other is nitrogen atoms kinetically trapped at the reaction zone near the interface, presenting a non-equilibrium state. These mechanisms have been validated by experimental data. Once permeated by nitrogen, the SiO₂ film dielectric constant increases proportionally with the nitrogen percentage.⁸ The benefit of nitrogen-permeated SiO₂ can be evaluated from the formula:

t_SiON=t_SiO2 (k_SiO2/k_SiON)

where t_SiON and t_SiO2 are the thicknesses required for the gate dielectric for SiON and SiO₂, respectively. k_SiON and k_SiO2 are the dielectric constant of SiON and SiO₂, respectively. The increased k relaxes the physical thickness constraint required for gate dielectric requirements.

Nitrogen incorporation can be classified as physical, chemical or thermal. Some of the physical methods for incorporating nitrogen into SiO₂ are ion-beam sputtering and nitrogen implantation. Generally, these methods have the benefits of low-temperature operation and a hydrogen-free film. The most commonly used chemical method is plasma-enhanced chemical vapor deposition (PECVD), which operates at a relatively low temperature (<400°C) and deposits SiON film directly onto silicon or an existing thin layer of SiO₂. Thermal method examples include the anneal of the oxide film in a nitrogen-bearing atmosphere (i.e., N₂O, NO, N₂ or NH₃). The two most commonly used methods are plasma and thermal NH₃ nitridation on a thermally grown oxide. Both provide good process control and a high percentage of nitrogen incorporation.

1. NH3 nitridation is the most critical step for converting oxide to oxynitride. The N2 anneal is used to drive out trapped H2, and the O2 soak neutralizes the silicon dangling bond.

Figure 1 illustrates a typical NH₃ nitridation process comprised of three steps. The first is a high-temperature NH₃ treatment, which incorporates nitrogen and hydrogen into the original SiO₂. This step is followed by a high-temperature N₂ anneal, which drives excess hydrogen from the film. The last step is a low-temperature O₂ soak, which stabilizes the SiON formed from the previous steps. Of the three steps, the NH₃ treatment is the most critical, as device performance is largely modulated and controlled by NH₃ concentration, temperature and time. During the NH₃ treatment, the ammonia reacts with SiO₂:

Si-O-Si + NH₃ > Si-OH + Si-HN₂ > Si-NH-Si + H₂O

The H₂O is purged out of the reaction chamber, while both nitrogen and hydrogen are incorporated into the film forming chemical bonds with silicon. While nitrogen incorporation is desirable, hydrogen is a byproduct of the reaction, and excessive hydrogen results in a positive interface charge,⁹ causing undesired device threshold voltage shifts and high gate leakage.

Gate oxynitride and process monitoring

Gate oxynitride is critical to device performance. It has been closely monitored through manufacturing operation at Metal 1 and end of line, typically using electrical test (E-test). Among the E-test parameters, threshold voltage for PMOS (V_tp), threshold voltage for NMOS (V_tn), gate leakage for PMOS (J_gp), and gate leakage for NMOS (J_gn) are the most important. These parameters are very sensitive to gate oxide growth and gate anneal process conditions.

2. Gate anneal process impact and correlation between Vtp and Vtn, showing oxide thickness and nitridation degree effect on device threshold voltage. Thick oxide reduces Vtp and increases Vtn. Heavy nitridation increases Vtp and reduces Vtn.

Figure 2 shows a typical gate oxide nitridation process condition impact on the E-test parameter. In a nitridation process, when the incoming wafer has a thick oxide, there will be less nitrogen penetration and incorporation, resulting in higher gate leakage. An incoming wafer with a thin oxide produces opposite results. For a given oxide thickness, increased temperature or NH₃ concentration raises nitridation levels, resulting in lower gate leakage and higher threshold on the PMOS (V_tp) shift. It is noted that V_tp and V_pn are affected by the same process conditions but with opposite results. This is explained by MOS' energy band structure. For a PMOS device with positive interface charges (as with SiON film) under a negative bias, when the device is turned on, it is under inversion, valance band (E_v) bands toward the Fermi level (E_f), and the result is an increased flatband voltage (V_fb) and a large threshold voltage shift (Fig. 3a ). In a NMOS device with positive interface charges under a positive bias, when the device is turned on and under the inversion state, the conduction band (E_c) groups toward E_f, resulting in a small threshold voltage shift in the opposite direction (Fig. 3b ).

3. Threshold voltage shift induced by positive interface charge. The energy band diagrams explain the opposite trends of Vtp and Vtn by nitridation process conditions, and reduced Vtn shift caused by reduced Vfb by positive interface charge. Increased Vtp shift caused by increased Vfb by positive interface charge.

While E-test parameters are good device performance indicators of gate dielectric characteristics, they are collected at the back-end-of-line (BEOL) operation in a wafer fab and cannot be used for real-time process control or monitoring. For gate oxide nitridation processes, the most important process variations are NH₃ concentration and temperature. A small variation of these can result in a significant shift of threshold voltage and large gate leakage. Ideally, the process is controlled and monitored at three levels: tool stability, process variation, and device performance. Tool stability can be monitored by measuring chamber temperature and NH₃ concentration using advanced process control (APC). Process variation control and device performance prediction need real-time monitoring.

Conventional surface analytical techniques can be used to measure nitrogen and hydrogen from a nitrided oxide film. The depth profiles show that nitrogen filled up at the original Si/SiO₂ interface, and hydrogen peaked at the free surface and dropped continuously. The lack of an interface pileup indicates that hydrogen atoms are not chemically bonded or trapped at the interface. Instead, they are concentrated at the film's surface, attracted by the surface states, and can diffuse through the film. Surface analytical methods provide in-depth information on hydrogen and nitrogen incorporation during the oxide nitridation process and out-diffuse afterward. This information is useful for process development and diagnostics, but these techniques only consider the chemical aspect and cannot detect electrical charge effects from process conditions.

A commonly used electrical analysis method is non-contact electrical technology. Here, test data provides correlation to device E-test data, enabling inline transistor performance prediction instead of waiting for end-of-line E-testing. In a typical application, the electrical charges at the oxynitride film surface and interface are measured and correlated to process conditions and device performance. Some useful parameters include differential tunneling voltage (DV_t) and V_fb. DV_t is used to monitor high-field leakage properties of the oxide and provide an indication of oxide integrity and quality similar to more traditional soft-breakdown measurements. Here, DV_t is measured by applying a large corona bias (positive and negative) until the surface voltage saturates at maximum. The DV_t is the sum of the two surface maximums. V_fb refers to the voltage at which there is no electrical charge in the semiconductor and, therefore, no voltage drop across it; in band diagrams, the energy bands of the semiconductor are horizontal (flat). In this technique, V_fb is the voltage at which the silicon surface photo voltage is zero (i.e., no electrical field in the silicon). Figure 4 is an example of DV_t's response to process conditions.

4. DVt response to temperature in a gate anneal process, showing good correlation between DVt and process temperature: DVt tracks process temperature well with adequate sensitivity.

Future gate dielectrics

As transistors shrink, gate dielectrics become thinner — a mere 1.2 nm, which is just five atomic layers thick. This brings gate design to almost the atomic structural level. Leakage through the SiO₂ layer of a gate increases exponentially as its thickness decreases. Nevertheless, making the dielectric ever thinner is necessary to meet increasing performance goals. When a transistor's gate dielectric thins, its insular quality decreases and current leaks through it; oxynitride works well for gate dielectric applications up to the 45 nm node. According to the ITRS, the electrical equivalent gate dielectric thickness must be <1.0 nm by 2010. This can only be done by using high-k dielectric materials, such as hafnium dioxide (HfO₂), zirconium dioxide (ZrO₂) and titanium dioxide (TiO₂), which all have a dielectric constant >3.9, SiO₂'s k.

High-k dielectrics must be thermodynamically stable on silicon, with respect to SiO₂ and MSi formation. They should have minimum high-k/silicon interfacial states and provide specific work functions for NMOS and PMOS devices. They must also meet dynamic requirement and etch selectivity criteria for manufacturing consideration.

High-k dielectric R&D began in the early 1990s. Potential materials are Al₂O₃, ZrO₂, HfO₂, TiO₂ and Ta₂O₅, with HfO₂ and ZrO₂ as the most promising. Both oxides provide the required dielectric constant and leakage, but suffer from low carrier mobility and threshold voltage instability. Further research determined that carrier mobility and threshold voltage shift are caused by phonon scattering and Fermi-level pinning. The higher the dielectric constant, the higher the polarization, creating surface optical phonon vibration that interferes with transistor channel electron mobility; Fermi-level pinning results when a high-k gate dielectric is combined with a polysilicon gate electrode. Gate dielectric/gate electrode interface defects induce relatively high threshold voltages, reducing drive current and impairing performance. High-k only works when used with metal gate electrodes with appropriate n+ and p+ work functions to improve the n-channel and p-channel room temperature mobility in the high-k dielectric (HfO₂) close to that of conventional SiO₂/polysilicon stack, like a mid-gap TiN electrode.¹⁰ Considerable reduction of gate leakage can be achieved with a properly designed high-k dielectric metal gate stack with a lower electrical equivalent gate dielectric thickness.

SiO₂ has served microelectronics applications with excellent physical, electrical and chemical properties. Oxynitride preserves SiO₂'s benefits and extends applications to the 45 nm node. Nitrogen incorporation during nitridation is a complicated process. Interface-trapped charges induced from the process play a vital role in gate dielectric integrity. Nitridation process control and monitoring is crucial to ensure process stability for desired device performance. High-k dielectric introduction must be combined with a metal gate electrode, which is currently a technical challenge.