The Gate Holds the Key

With the industry facing significant challenges to further shrink device technologies below 65 nm, things are simply not the same anymore. One of the key issues to tackle is the gate stack. While the introduction of a high-k material as a gate dielectric has been delayed, many alternative approaches are starting to appear, especially for the short and medium timeframe.
 
Further reducing oxide thickness using nitrided SiO₂ as a gate dielectric, in combination with polysilicon for the gate, faces serious difficulties below the 65 nm node. Originally, the strategy to follow looked clear enough, replacing both gate and oxide materials with new ones to keep up with roadmap scaling while maintaining electrostatic integrity and sufficient drive current.

In fact, improving transistor performance can be done either by introducing new materials or drastic architectural changes. Deposition of silicides on top of source/drain and gate is an example, which results in lower sheet and contact resistance. Ultrashallow junctions are assumed to lower sheet resistance and suppress short-channel effects.

Introducing strain in the channel has been widely accepted as a way to boost chip performance with the need for aggressive scaling of gate length and oxide thickness. The reason is that strain results in higher carrier mobility and reduced source/drain resistance and, as a consequence, in higher performance.

Alternatively, transistor performance can be increased by reducing the gate lengths and increasing gate oxide capacitance per centimeters squared. The problem associated with this approach (i.e., increased current leakage) may be tackled by using high-k materials instead of conventional SiO₂ or nitrided SiO₂ for the gate dielectric. But that is only part of the problem. Because of the incompatibility of the high-k material with the polysilicon gate, the gate electrode needs to be replaced by fully silicided (FUSI) or metal gates. A way out could also be the introduction of alternative device structures such as multi-gate devices (MuGFETs), since they would yield better scaling properties than conventional bulk devices for the 32 and 22 nm nodes.

Introducing new materials has always been quite a challenge in the semiconductor industry. Using high-k dielectrics with metal gates has been demonstrated to do the job, but the complexity of getting up to yield and reliability requirements is not yet fully investigated, especially for high-performance applications. This issue will determine if and when metal gate/high-k dielectric gate stacks will be introduced into manufacturing.

Meanwhile, the industry will stretch today's technologies to extremes and follow an evolutionary path rather than a revolutionary route, much like the optical lithography story where a wavelength generation is extended over several technology nodes by using resolution enhancement techniques instead of adopting other patterning techniques.

In this way, 45 nm will be a scaled-down version of 65 nm for the gate stack, so there will be no metal gate and no high-k material as dielectric layer, except maybe for some specific applications (e.g., ultralow-power control circuitry for displays, where performance is not the prime issue).

The next node is a different story. For 32 nm, the industry has not yet made a choice. Consumption of the polysilicon gate by full silicidation could be a solution, and much research has been done in this area. By combining other techniques, such as strain engineering and ultrashallow junctions, carrier mobility and performance can be improved considerably. The introduction of strain can be done by using strained-compressive or tensile-contact etch stop layers for PMOS and NMOS devices, respectively. It can also be done by using recessed-strained SiGe in the source/drain areas to create uniaxial strain in the channel; both approaches combined are also under investigation. As mentioned, MuGFET devices show more promise to scale down further than conventional CMOS. Performance of these devices can be further increased by inducing stress, but gate stack issues are more similar than on planar devices.

The industry will eventually have to do the math and evaluate economical benefits vs. the risk of introducing such a disruptive technology. And it is already clear that the use of high-k dielectrics will reach its limits in the scaling roadmap. That is why research is carried out to introduce materials such as III-Vs for NMOS and germanium for PMOS on silicon, because they are known to yield better-performing transistors.

There is still a long road to go before this will happen. Meanwhile, the search for altered or new transistor devices goes on, bringing their own consequences to other aspects of the semiconductor value chain, such as design issues, changing libraries, and related technologies and tools. As a result, a shift toward these devices will be much more than a reliability issue; not in the least an economical one.