Ge Epitaxy on Si: An Enabling High-Performance CMOS Platform

The drive current for germanium PMOS transistors is slightly enhanced relative to strained silicon made by selective epi of SiGe. Standard silicon epi reactors can be equipped with suitable germanium precursors to fabricate germanium on silicon (GOS) wafers.

C. Werkhoven, C. Arena, M. Bauerand P. Brabant, ASM America, Phoenix, Ariz.; M. Meuris, V. Terzieva and L. Souriau, IMEC, Leuven, Belgium -- Semiconductor International, 10/1/2006

Strain engineering is a well-accepted manufacturing technology for CMOS devices to enhance the mobility of charge carriers in the silicon channel, resulting in impressive drive current improvements. One early approach uses high-stress silicon nitride films deposited over the gate, but the resulting strain becomes less effective when the gate size is reduced. The reverse is true when selective epitaxy of strained silicon germanium (SiGe) is used to replace the area around the gate.¹ Only when strain is induced on a global rather than a local scale are geometry effects avoided. Strained silicon on insulator (sSOI) wafers represent a well-characterized example for NMOS transistors.² In all cases, however, strain effects will saturate and new channel materials with higher mobility will be introduced.

Relaxed germanium

A prime candidate for such a new channel material would be germanium because it can have mobility as high as 1900 or 3900 cm²/Vsec for holes and electrons in bulk germanium material, respectively. This is 2-4× higher than the corresponding values in bulk silicon material. Moreover, germanium can be considered as being the closest to silicon when it comes to physical and chemical properties.

The development of high-performance transistors in germanium wafers is reasonably successful, at least for PMOS transistors. In general, NMOS transistors fall short of expectations and are therefore not suitable to include in this study.

The availability of germanium wafers at the right size and cost is, however, of great concern, considering the limited abundance of the corresponding raw material. In addition, the increased weight and brittleness of germanium wafers hampers the use of production-proven processing equipment. Hence, it is very beneficial to capitalize on the existing device manufacturing technology and integrate germanium in a suitable way using silicon wafers as a platform.

Germanium on silicon (GOS) epitaxy is a low-cost, straightforward method to obtaining the wafer size and material quality desired. Alternatively, layer transfer technology is currently used in high-volume manufacturing of SOI wafers, and this approach can also be used to produce germanium on insulator (GOI) wafers, provided the insulator wafers do not inhibit the targeted application.

Germanium epitaxy

There are suitable germanium-containing precursors available, such as germane (GeH₄), di-germane (Ge₂H₆) and germanium tetrachloride (GeCl₄), which enable the growth of very uniform epitaxial germanium layers with a high growth rate. Of particular interest is the tendency of germanium to grow into 3-D islands, because the strained nuclei tend to lower their energy by a thickness- and temperature-controlled plastic relaxation. This can be avoided by seeding the silicon at low temperatures (<400°C) with a homogeneous germanium layer and optimizing the relaxation process. The seeding step is followed by growth at much higher temperatures (>650°C) to make sure the final layer thickness is achieved in the shortest possible time. This also guarantees that layer properties as well as costs will meet expectations. Typically, a layer thickness uniformity of >1% is achieved, and these numbers are comparable with silicon epitaxy.

Introducing both n-type and p-type conductivity is a capability of critical importance to the fabrication of CMOS devices. In situ doping during growth is a powerful method to achieve high carrier concentrations without the complexity of ion implantation and subsequent anneals needed to activate the dopant atoms and reduce the implantation-induced defects. With standard dopant gas concentrations of phosphine, arsine and diborane, resistivity can be controlled in the range of 1 W-cm to 1 mW-cm, or a carrier concentration in the range of 1 × 10¹⁶ cm^-3 to 5 × 10¹⁹ cm^-3. Typically, the uniformity of the resistivity is >2% at 3 mm edge exclusion, very similar to state-of-the-art uniformity in silicon epitaxy.

Extreme care has to be taken to reduce the moisture and oxygen contamination in the growth system because, at low temperatures, oxygen will be more easily incorporated than at high temperatures, which can lead to undesirable defects at the interface and in the layer. The Epsilon epitaxy system used in this study is advantageous when it comes to the handling of highly purified gases and avoidance of contamination from air leaks, which are important to enabling high-quality growth at low temperatures.

Dislocations

Of particular importance to consider in the manufacture of GOS wafers is the fact that the lattice constant of silicon is 4.2% smaller than that of germanium. As a result, misfit dislocation segments quickly form at the interface between the germanium layer and silicon substrate in order to accommodate the difference in lattice size, even after only a few monolayers of growth. Since misfit dislocation segments cannot end inside the crystal, such segments usually turn into threading dislocations that move with the growing layer and end up at the surface. Such dislocation can adversely affect the electrical properties of CMOS devices when penetrating the active areas of transistors.

Fortunately, threading dislocations typically annihilate during growth, which means that it is beneficial to grow layers of several micrometers in thickness in order to maximize the annihilation process.

1. TEM of a germanium on silicon (GOS) wafer (left) shows the misfit dislocation network at the Ge/Si interface, which usually manifests as threading dislocations at the GOS wafer surface (right), which is evident after defect etching.

All these phenomena are clearly visible in the high-resolution cross-section TEM graph of the GOS wafer (Fig. 1). In the same figure , a SEM image shows the surface after so-called selective defect etching. This provides not only a statistically more realistic count of the dislocation density, but it also represents the surface regime, which is where devices will be made. The dislocation density observed for undoped germanium of 1 µm thickness, grown with a non-optimized seeding and bulk layer growth process, turns out to be in the range of 10⁷-10⁸ cm^-2. Further annihilation of dislocations is observed by varying the mentioned parameters of seed and bulk layer growth, the nature of the dopant and the way it is introduced, and a variety of other growth and post-growth parameters.

Surface roughness

An atomically flat surface is extremely important for good CMOS device performance so that a high-quality gate oxide can be formed. Figure 2 shows a comparison between atomic force microscopy (AFM) measurements for a bulk germanium wafer and a GOS wafer with a germanium layer of 1 µm thickness. The corresponding numbers reveal that as-grown GOS wafers have the same surface roughness (i.e., <0.35 nm RMS) as a polished germanium wafer, and can thus be used for CMOS processing “as is.”

2. The AFM surface roughness values for GOS (left) and bulk germanium wafers (right) are 0.36 and 0.35 nm RMS over a 2 × 2 µm area.

This excellent surface quality was obtained via precise optimization of the seed growth parameters and subsequent ramp conditions from the seed layer growth temperature to that of the bulk layer. Care needs to be taken to avoid creation of layer discontinuities and non-uniform growth. Surprising is that there is no cross-hatch pattern on the GOS wafers — a phenomenon very commonly observed when growing SiGe on silicon that is believed to have originated from a misfit-induced growth inhomogeneity. The absence of cross-hatch in GOS wafers may be attributed to the very narrow spacing between the misfit dislocations at the interface (every 24th crystal plane is missing).

Germanium devices

A special process developed at IMEC was used to form a high-quality interface layer for the gate dielectric for which HfO₂ was selected. The HfO₂ was deposited by atomic layer deposition (ALD) using the ASM Pulsar reactor combined with a metal electrode.³ The drive current for germanium PMOS transistors is significantly higher than that of unstrained silicon using the same gate stack, but only slightly enhanced compared with strained silicon made by selective epitaxy of SiGe (Fig. 3 ). The higher current can be attributed to the higher mobility of holes in germanium compared with unstrained silicon (i.e., a mobility of ~200 cm²/Vsec for HfO₂/Ge gates with equivalent oxide thickness values in the range mentioned in Figure 3 can be derived from our measurements). This indicates that, compared with silicon, PMOS devices in germanium do not exhibit anomalous surface or defect scattering effects that cause a more-than-expected reduction of the mobility in the channel.

3. The drive current for germanium PMOS transistors is significantly higher than that of unstrained silicon, but only slightly enhanced compared with strained silicon made by selective epitaxy of SiGe.

Separate leakage current measurements using large-area diode structures reveal higher values for GOS wafers than observed for bulk germanium wafers. Considering the presence of threading dislocations in the former case, this is more or less expected, but other process-related contributions cannot be ruled out at present. Alternatively, germanium can be grown selectively in the active area of transistors, which introduces a very effective dislocation annihilation mechanism. These and other results will be reviewed in future communications.

Outlook

Atomically flat and very uniform germanium layers can be grown directly on silicon using a standard silicon epitaxy reactor equipped with suitable germanium precursors. State-of-the-art PMOS transistors made in GOS wafers show very substantial drive current improvements over unstrained silicon. It is expected that further developments in the growth and processing technology will qualify GOS for PMOS transistor applications.