Dopant Fluctuations Affect High-Frequency LER Requirements at Nanoscale

As shrinks continue, transistors' fundamental electrical properties are changing. LWR andLER requirements will also be affected, as dopant concentration impacts nano roughness.

Daniel J.C. Herr, Semiconductor ResearchCorp., ResearchTriangle Park, N.C.; Alain C. Diebold,Sematech, Austin, Texas -- Semiconductor International, 9/1/2006

Measurement and control of line edge roughness (LER) and linewidth roughness (LWR) for transistors is driven by the need to provide uniform electrical properties across the chip and from chip to chip.^1-5 Scanning electron microscopes (SEMs) and atomic force microscopes (AFMs) designed for critical dimension (CD) measurements can determine LER and LWR in patterned photoresist or patterned polysilicon gate structures.⁵ The key attribute of LER is the spatial frequency and amplitude of the roughness (Fig. 1 ).^5-8 This roughness results in nanoscale variations in the gate length of a transistor. Reports indicate that both off-state leakage current and saturation drive current are impacted by LER.^5-8 As transistors are scaled to smaller gate lengths, the physics behind the need to control LER is changing along with a considerable tightening in control requirements.

Saturation takes over

The switching speed of transistors is largely controlled by the drive current of the NMOS and PMOS transistors. When the gate length of a transistor was larger than it is today, shrinking the gate length, increasing the carrier mobility, and decreasing the gate oxide thickness were all means of increasing the drive current. This is the so-called long-channel behavior of a transistor. When transistor gate lengths shrink below 10 nm, the drive current is controlled by the saturation velocity of the electron or hole in a material. Control of transistor gate length will be important because of its impact on the threshold voltage of the transistor. A dual-gate transistor with a 5 nm gate length, 2 nm channel thickness, and gate dielectric thickness of 1.5 nm requires CD control to be ~0.2 nm with a measurement precision of ~0.1 of the 0.2 nm.⁹ Imagine controlling CD variation to dimensions of the length of one atom or less. Today, transistor behavior is shifting between these two extremes.

The discussion about the impact of dopant nano roughness on device properties is just now beginning to take place. Here, dopant roughness at the source-channel and channel-drain interfaces is used to discuss projected high-frequency LER requirements. One of the authors first proposed this issue to the International Technology Roadmap for Semiconductors (ITRS) community, and we expect to further the discussion in this article. The first step is a comparison of LER requirements for the polysilicon gate with the projected interfacial roughness at the channel-source and channel-drain interfaces. The comparison assumes a random and sparse distribution of dopant atoms throughout the interface region. It also considers the implications with respect to projected functional LER specifications.

1. Schematic of active source-channel-drain regions, with the location of the natural dopant wavefront at the source-channel and drain-channel interfaces. (Source: ITRS)

The ITRS projects technology requirements over a 15-year horizon. In many cases, the requirements are based on scaled extrapolations of current technology needs. The 2005 revision of the LER roadmap is considering high-frequency (HF) LER specifications of 2.6 nm in 2005, scaling to 0.5 nm in 2020.^1,2 These HF LER targets correspond to length scales on the order of ~11 and ~3 atoms of roughness in 2005 and 2020, respectively.^1,2

The device's perspective

It is useful to look at these length scales in terms of the atomic-sized features in a transistor. Figure 1 represents a schematic of a MOSFET's source, channel and drain structures.

The uniformity of the electric fields surrounding the charge carriers depends on the dopant concentration. For example, charge carriers within the heavily doped source and drain regions experience fairly homogeneous local field environments.^10,11 When electrons leave the source with energies (within 4.02 eV) close to the vacuum level, at 0 eV, they will reside in the conduction band.¹⁰ This sea of electrons serves as a reservoir for charge carriers of information through the channel. When the electron states are clustered at the lower edge of the conduction band, E_c, the interdopant spacing within the bulk source is ~33.1 Å. The ambient concentration of electrons within a bulk source is ~2.75 × 10¹⁹ electrons/cm^-3,¹¹ and the corresponding concentration of active dopants should be similar, as they serve as the source of these charge carriers.

When the dopant concentration is lower, the electric field experienced by the charge carriers is less uniform. This is the case at the interface between the channel and source or drain. Consider the case for which the active interface dopant concentration reduces to about half of that in the source. This implies an interface density of ~1.38 × 10¹⁹ active dopants/cm³ and a spacing between active dopants of ~41.7 Å. This spacing induces a natural roughness in the active dopant wavefront at the boundary between the source and channel regions (Fig. 2 ).

2. Schematic of natural roughness at the source-channel active dopant wavefront. (Source: ITRS)

For this example, when the interface active dopant density is approximately half of that in the bulk source, then the magnitude of this natural dopant wavefront (NDW) roughness is ~36 Å. Similarly, if the active dopant concentration at the NDW is defined to be 10% of the bulk source concentration, then the corresponding NDW roughness would be ~62 Å. Even if one assumes a vertical concentration drop at the edge of the bulk source region where the active dopant spacing is ~33 Å, the NDW roughness would still be ~29 Å.

The implications for all of this are as follows: The 2005 ITRS projects microprocessor unit (MPU) physical gates lengths of 32 nm in 2005 and 5 nm by 2020. The corresponding LER requirements are projected to scale from 26 Å (3σ) in 2005 to 5 Å (3σ) in 2020. For the examples given above in which the NDW roughness ranges from ~36 to ~62 Å, it is difficult to infer the relative impact and significance of the projected LER tolerances on the device performance and variability. In the near term, projected LER requirements appear to be similar to the estimated NDW roughness cited above. This suggests that lithographically induced roughness and NDW roughness may synergistically impact device performance and variability. Deconvolving these effects requires a collaborative study between the patterning and device communities. A closer examination of the interdependence between NDW roughness and LER may reveal specific critical and coupled factors that drive device performance and variability for specific device technologies. Such a study may also help the ITRS community establish guiding principles for defining projected functional roughness requirements.

Toward the end of the ITRS, NDW roughness — ~3.6 to ~6.2 nm — may be similar to the MPU physical gate length of ~5 nm, and more than an order of magnitude larger than the projected LER tolerance requirement of ~5 Å. As we approach the 5 nm node, will non-lithographic roughness factors dominate device performance and variability? One could imagine active NDW dopants influencing transiting electrons as they accelerate toward the channel. Engineering these trajectories would be difficult with existing fabrication methods. However, this could change if manufacturable technologies are developed that enable tighter control over gradient and interface structures. Consequently, the current projected end of the ITRS LER requirements could become significant when manufacturing solutions exhibit atomic or near-atomic placement control of active atoms within a laterally directed interface structure.

As device dimensions continue to shrink, the fundamental electrical properties of transistors are changing. The switching times for nano transistors will depend on the saturation velocity of carriers in the channel. Process tolerances will also approach or seem to exceed atomic dimensions. LWR and LER requirements will be impacted. It has been determined that dopant concentration impacts nano roughness in the interface between the source (or drain) and transistor channel. The dimensions of this roughness are similar to those expected from lithographic processing. Deconvolving the relative influence of each on a transistor will be difficult at best.