FSA Panel Explores Design Requirements for SiP

John Baliga, Contributing Editor -- Semiconductor International, 9/1/2006

Test and Assembly/Packaging was one of the four TechXPOT presentations at SEMICON West this year, indicating that it is an area requiring attention on par with that paid to the other three: Emerging Technologies, Manufacturing Productivity and Effectiveness, and Challenges in Device Scaling. As a part of it, the Fabless Semiconductor Association (FSA) held a timely panel discussion about system-in-package (SiP) issues.

The SiP is gaining prominence, and it poses significant challenges, especially for fabless companies. The two main challenges addressed by the panel were chip-package codesign and design for test (DFT).

Designing a SiP is a complex task now done by the most experienced engineers using custom design flows. Currently, this limits the number of SiP design starts. For SiP designs to increase, chip-package codesign capabilities and collaborative design capabilities must both improve. One of the main themes of the panel was to advocate and encourage work on specifying codesign and DFT requirements for EDA tools. EDA suppliers cannot be expected to realize the necessary improvements without them.

Since there are so many options in designing SiPs, absolute standardization must be done wherever it can. For example, form factors and I/O layouts would have to be standardized for commodity die like memory. No mention was made of a standardized grid, though it might be an interesting idea to revisit.¹

Even with things like standardized outlines, the large number of SiP design options will require a great deal of capability from design tools. Wire-bonded stacks, through-silicon vias (TSVs), bump attachment, and integrated passives are among those options. In addition, the ultrathin die that are now used are more sensitive to thermal and mechanical stresses. It may be necessary to model how the package affects these die at the transistor level. Design tools will have to deliver a great deal in terms of codesign capability.

Testing is a very important and complex issue. It would be nice to use commodity die and passives that come fully tested and burned in. In the most general case, though, decisions would have to be made about how well each die, passive component, and substrate layer must be tested in an overall test strategy for each SiP. Not only must each component be designed for test, but the overall design must account for testing.

Of course, final test is a part of the overall test scheme. The assembled SiP would have to be tested, and the SiP should be designed to make that testing as efficient and effective as possible. One aspect of final test is connectivity, in which it is verified that all the components are connected. If one of the components is a three-dimensional IC in which multiple die are connected with TSVs, the question about when connectivity is test arises. Should the 3-D IC be fully connection tested before packaging, or can this be done at final test?

Maybe final test should also verify full connectivity within the 3-D IC in any case. If so, design for final test would be a part of die design. This is just one of the many possible questions that could be asked, and it reveals the depth to which DFT must reach for high-volume SiP production to be a reality.

In addition, codesign and DFT capabilities must be flexible. The wide range of options makes this necessary. The nature of this flexibility must be specified as much as possible very soon if EDA suppliers are to have a chance at providing it.

Since multiple companies will likely be involved in SiP designs, distributed design will have to be supported. That is, a chip design team, a package design team, and a board design team need to be able to work on the same chip-package-board design in real time, even if all the teams are in different locations. This may be a moderate challenge compared with the others that EDA providers will face, but it may be a considerable challenge down the road.

As SiP designs get more complex, it is not unreasonable to imagine that “what if” examinations in the near future will resemble the finalized collaborative designs of today. In other words, a nearly complete collaborative design might have to be done just to determine the feasability of a proposed project. In this type of environment, intellectual property (IP) protection would be more “interesting.”

Companies would constantly be using the best of their IP in collaborative design examinations with prospective partners, making the protection of their IP more of a challenge. The identification of best practices for collaborative SiP design would have to account for this.

This type of scenario bears some resemblance to some of the business problems that e-manufacturing tools were designed to solve: providing high visibility while maintaining propriety. It would be interesting to see if some of that knowledge could be leveraged.

Cost and time-to-market are reasons for using a SiP design over a system-on-a-chip (SoC) design, and sometimes it is an inability to reliably package an SoC version of a design. It might just be that SiPs will drive the innovations needed to design all future electronic devices, including SoCs.

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