200% pMOSFET Mobility Gain With Strain
Peter Singer, Editor-in-Chief -- Semiconductor International, 9/1/2006
Researchers at Applied Materials (Sunnyvale, Calif.)
and IMEC (Leuven, Belgium) have demonstrated a remarkable 200% gain in mobility in pMOSFETs through the use of strained silicon. Devices with a 45 nm gate length were fabricated with recessed source/drains made of silicon germanium (20% germanium) and nitride contact etch stop stressor films showed nearly 200% improvement in hole mobility compared with equivalent transistors with no strain. The work was reported in IEEE
Electron Device Letters in June, and presented at a press conference
during SEMICON West . “This is really dramatic evidence that performance-scaling is shifting from physical scaling to the use of materials to keep the gains accruing consistent with Moore's Law,” noted Tom St. Dennis, senior vice president and general manager of Applied Materials. “Some of the things that are keeping the industry moving at a pretty high innovation velocity and creating new market opportunities for the equipment industry are related to using materials to achieve next-generation device performance, including drive current and mobility gains.”
Although the 200% gain is notable, the advantages of strained silicon are already well known. Virtually all major logic companies have had it in development, and have or will soon have it in production. The same is true of most foundries, which are either sampling strained silicon or offering it in production. “You can shrink the transistor gate length, but it's not giving you the Idsat performance or the gain performance that you've got to get. You're going to start consuming, instead of 100 W per chip, you'll be at about 1000 W per chip, and you won't be able to continue scaling,” St. Dennis said.
The strained silicon devices fabricated in this work started with a standard process flow up to the heavily doped drain junctions using a 1.4 nm plasma-nitrided gate dielectric and a polygate electrode. After source/drain implants and anneal, the source/drain was etched 25-120 nm deep, either isotropically or vertically, and filled with selectively deposited boron-doped SiGe. After nickel silicidation, either a 50 or 100 nm compressive contact etch-stop layer was deposited (Fig. 1). The interesting news is that the combined effects of the stressors is larger than the additive gains.
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| TEM of PMOS with SiGe in the source/drain and a compressive contact etch-stop layer. Stress contours are shown on the right. |
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