Deep Silicon Etching Gets Ready for 3-D ICs
3-D interconnects require robust through-silicon via etchers capable of uniform profiles, wafer-to-wafer repeatability and high productivity.
Laura Peters, Senior Editor -- Semiconductor International, 9/1/2006
Consumer products such as digital cameras, PDAs and cell phones, along with next-generation servers, are driving the need for product miniaturization: increased functionality, increased storage capacity or both in a smaller package.1 To meet this requirement, many device manufacturers are investigating 3-D interconnect technology to stack die or wafers. 3-D interconnects are driving new requirements for processing tools including deep silicon etching, wafer thinning and wafer bonding. Deep silicon etch is used to form through-silicon vias and connect stacked die or wafers.2 Deep reactive ion etch (DRIE) systems have been used for a number of years in the manufacture of microelectromechanical systems (MEMS).3 With the introduction of through-silicon via etching for 3-D integration, the requirements for DRIE equipment are much tighter, especially in the areas of tool productivity, uniformity of profiles across the wafer and process drift.
“One important equipment parameter is throughput because, ultimately, manufacturers are trying to get a better device by doing wafer-level packaging in the first place. So they are weighing the device performance gain vs. the increased cost of wafer processing technologies,” said Dave Thomas, marketing manager of etch products at Aviza Technology (Scotts Valley, Calif.).
But even with very productive processes, the cost-effectiveness of 3-D approaches themselves have not been proven. “The cost benefit associated with 3-D integration is unclear,” said Susan Vitkavage, the project manager for 3-D interconnects at Sematech (Austin, Texas). “And to date, there is not a roadmap for through-silicon vias, the aspect ratios and dimensions that are needed, and by what date, which will depend on whether you're talking about a high-performance part vs. a handheld part, for instance.” Sematech is developing this roadmap and performing in-depth cost analyses to determine exactly what kinds of cost targets the manufacturers of DRIE, wafer thinning and other 3-D tools need to meet. They are also comparing the cost effectiveness of wafer-to-wafer bonding approaches vs. die-to-wafer appoaches.
The drivers
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| The 2300 Versys etch system for 200 and 300 mm through-silicon via applications is specifically designed to meet the needs of advanced 3-D integration. (Source: Lam Research Corp.) |
The industry still awaits a commercial success to fuel 3-D integration efforts. For example, earlier last year, Infineon (Munich, Germany) announced intentions to integrate a two-chip stack in a credit card application. Later, the company announced it was not going to take the product to market, though it claimed no problems with the chip stacking technology.
A good example of 3-D integration at the front end of line (FEOL) is IMEC's (Leuven, Belgium) introduction of through-wafer vias after FEOL and before BEOL processing, using silicon wafer thinning to as low as 20 µm and 5 µm copper “nails.”4 The process (Fig. 1 ) used a silicon carrier wafer during grinding and polishing and a Cu-Cu thermo-compression bonding process.
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| 1. Optical images of the backside of a wafer with through- wafer vias after thinning to 17 µm by backgrinding and polishing. After silicon CMP (left), copper smearing is evident. A non-selective slurry removed the residue (right) (Source: IMEC) |
Today, WLP is applied in three forms: through solder bump redistribution on the die surface, encapsulation, or with through-hole technology. Silicon through-hole technology allows unprecedented silicon efficiency by drilling holes from the front-side to the backside pad interconnects. But with aspect ratios as high as 50:1, these etch processes can take a half hour or longer per wafer. To drive overall productivity, equipment suppliers need to provide systems with high availability, fast etch rates and a low cost of ownership.
To initially enable the very high etch rates and high-aspect-ratio etching, companies license the Bosch process, a patented process developed by Robert Bosch GmbH in 1996.5 Using an inductively coupled plasma (ICP) source, this time-multiplexed etching process consists of alternating etch and passivation (CVD) steps using SF6 then C4F8 gases. By controlling the degree of sidewall passivation, a nearly perfect anisotropic etch (with 90° sidewalls) can be accomplished. However, it is important to note that alternatives to Bosch etching and sources other than ICP sources are being used to achieve high-aspect-ratio etching of silicon.
The SF6 process gas uses fluorine atoms to etch the silicon surface isotropically, though the lateral etch rate is limited. Silicon etch rate is a function of both the rate at which reactive species generated by the plasma diffuses to the etch front and the rate at which etch byproducts diffuse from the surface. Each C4F8 polymerization step deposits a uniform layer of polymer isotropically on the wafer. The mask is typically photoresist or thermal oxide.
Integration approaches
Many of the devices in consideration today for wafer-level packaging use via sizes of 20-50 µm with depths of 80-170 µm. Advanced research is driving toward 5 µm vias with ARs up to 50:1. The etch process must be highly precise in these applications, driving stringent requirements in etch uniformity, profile control, critical dimension control, chamber matching and wafer-to-wafer reproducibility.
A variety of integration schemes are being investigated for through-silicon vias, which is not unexpected in an immature market. Jackie Seto, managing director for software, MEMS and packaging at Lam Research Corp. (Fremont, Calif.), explained: “Because the processes are very new, most companies haven't fully established their integration scheme. It's similar to when copper dual damascene was introduced in the mid- to late-90s. For equipment companies, every change in the integration can have a large effect on the unit processes. For example, some interconnects are formed by drilling from the top of the wafer down. In this case, it is critical to control the profile at the interface of the oxide and silicon. Another option is to form the via from the back of the wafer after the wafer has been thinned. Undercutting of the profile is not an issue with this integration scheme, but there is the added complexity of a stop layer, which could be a number of films including dielectrics or metals. So the integration scheme chosen will have a profound effect on the handling of the wafers and the equipment set.”
Phil Garrou, general consultant at RTI International (Research Triangle Park, N.C.), explained the different integration options. Through-vias can be fabricated as part of the FEOL process, in the same manner as deep trench capacitors are formed in the silicon. After processing, the wafers are thinned to expose the vias (typically tungsten), then interconnected to other die.
Alternatively, through-vias can be part of the BEOL interconnect scheme. Exclusion zones are left for the vias during design and fabrication of the IC. Foundry or packaging houses later etch the vias before mounting on the handle wafer and thinning (via-first) or after attachment of the second die or wafer (via-last).
Finally, if the chips have already been designed and fabricated and have not been prepared for 3-D integration, the vias can be redistributed to the area between the peripheral pads and dicing street.
Equipment performance
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| 2. A 50 µm (150 µm deep) through-wafer via being used in a production 3-D application. Etch rate was 15 µm/min. (Source: STS) |
Dean Malta, microfabrication manager at RTI International, gave an idea of state-of-the-art capabilities of DRIE systems: People are doing 20:1 aspect ratios in production, but 50:1 has been demonstrated. Selectivity to photoresist or oxides in excess of 100:1 is possible. Etch rates are routinely 20 µm/min and as high as 40 µm/min. With very high etch rates, surface roughness increases and, with a large etched silicon area, the inhomogeneity of the etch depth will increase. “So whenever you optimize one parameter, you tend to have tradeoffs. For instance, when you optimize sidewall smoothness, you might sacrifice etch rate or other characteristics,” he said.
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| 3. The quality and properties of the etched feature (40 x 100 µm) largely determine the effectiveness of the subsequent PECVD oxide dep/etch, PVD Ti, and PVD Cu seed layer and fill (fill not shown). (Source: Aviza Technology) |
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| 4. Etched vias in silicon of various diameter and aspect ratio. (Source: RTI International) |
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| 5. 2.5 µm vias that are 180 µm deep (~50:1 AR) (top) and 20 µm vias that are 442 µm deep (~22:1 AR). (Source: Unaxis) |
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| 6. 3-D test via etched through oxide (top) and silicon (bottom) layers. (Source: RTI International) |
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| 7. 3 µm through- silicon via structure taken 15 mm from the edge of a 300 mm wafer. (Source: Lam Research Corp.) |
Malta talked about a further issue with notching, which occurs when the silicon clears and the etch stops on an insulating layer like oxide. “You get a buildup of charge on the insulator surface, resulting in ion deflection and lateral etching. There are equipment options to deal with that, including additional power sources. Or you can go to a two-step approach, which begins with a typical etch process and finishes with an SOI process,” he said.
Ed Ostan of Unaxis (St. Petersburg, Fla.) explained some of the dynamics of controlling the etching process. “The process conditions, pressure, flows and power are very different during the etch than the deposition. So you have to have solid-state matching of the plasma to the power supplies, which stops you from having to move the hardware back and forth, and you also need an independent controller that marches all these components in unison,” he said.
With high-aspect-ratio etching, the industry mostly depends on timed etches, though there are some in situ monitoring techniques in the works. For instance, Horiba (Edison, N.J.) offers a polarimeter that can monitor wider features (80 µm) in situ. Then there are infrared systems that rely on back reflection.
“A lot of people will tell you the main criteria for performance is etch rate, and certainly it is important, but you have to take it in context because, depending on feature size, open area, you can get any etch rate you like,” Thomas said. He contends that company differentiation comes from the areas of process stability, maintenance, uptime and chamber conditions.
Productivity
Cost is a key driver for any new process. There is intense pressure to bring down the cost, not only of the silicon etch process, but also of the entire via processing module. This includes the etch, dielectric deposition, dielectric etch, physical vapor deposition (PVD) liner, seed and fill processes.
“Most of our patents for deep silicon etching have focused on the reliability of this etch, from the reliability of the endpoint to pressure control to stopping on the SOI and RIE lag elimination,” said Chris Constantine, chief technology officer of Unaxis. “We're trying to improve the production-worthiness of this etch so that we can do wafer production with these techniques.”
Jean-Marc Thevenoud, product manager of the Micromachining Systems Product Group at Alcatel Vacuum Technology (Annecy, France), noted that, through reduced C3F8 consumption, the addition of a heated liner, a new electrostatic chuck, and improved hardware and process knowledge, the DRIE process has been made much more efficient.
200/300 mm?
There is still a question over whether wafer-to-wafer or die-to-wafer bonding will prevail as the dominant approach to integrating chips. “From the beginning of this, a lot of folks wanted to say we're going to go all the way from the start with wafer-to-wafer. But we've done thorough studies looking at the economics. And the problem, aside from the fact that you have to hold a 0.5 µm tolerance across a 300 mm wafer, is that there's no way to line up the bad chips, so you take an exponential yield hit because every good chip takes out a bad one,” Garrou said. “We've concluded that it's much better to do a die-to-wafer with only known good die positioned on top of KGD, so there is no yield hit.”
But Sematech's Vitkavage said that, despite the high productivity of pick-and-place tools, there are cases where die-to-wafer will not make sense. “If you have a 300 mm wafer with a bunch of tiny die, you just can't populate that wafer in a reasonable period of time. We're putting numbers around that, and trying to understand where it does and doesn't make sense to take certain approaches.”
| For more information... | ||
| When you contact any of the following manufacturers directly, please let them know you read about them in Semiconductor International. | ||
| Alcatel Vacuum Technology | ||
| Aviza Technology | ||
| Lam Research Corp. | ||
| Surface Technology Systems | ||
| Ulvac | ||
| Unaxis | ||
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