Immersion Changes Litho Cluster Qualification
New interactions between water, resist and the lithography cluster (coater, scanner and developer) have consequences in several areas of process control.
Irfan Malik and Becky Pinto, KLA-Tencor Corp., San Jose, www.kla-tencor.com -- Semiconductor International, 9/1/2006
Immersion lithography, a key enabling technology for 65 nm design rules and beyond, has been on an accelerated development ramp for the past couple of years. With most of the major semiconductor companies installing their first immersion lithography (i-litho) cluster now, examining the effects of immersion technology on litho cluster qualification procedures is a timely and important pursuit.
The main differences in tool qualification procedures introduced by immersion technology stem from the fact that the wafer and scanner are coupled through water, introducing interactions between water, resist, topcoat and scanner. These interactions have consequences in several areas of process control. This article focuses on how changes in patterned defectivity, blanket film defect signatures, edge defectivity, overlay error and CD variation affect qualification of the i-litho cell.
Patterned defectivity
Characterization of patterned defectivity has become an integral part of litho cluster qualification. For immersion lithography, the interaction with water leads to immersion-specific defectivity as a function of process, materials and products. Since each fab has a unique combination of materials and products, its litho cluster qualification process would likewise be unique. Furthermore, the i-litho cluster qualification process would vary by layer (gate, contact, isolation, metal — typical layers used by logic manufacturers for immersion technology) because resist/topcoat stacks are layer-specific.
Fabs will also need to establish a baseline i-litho scanner qualification process, which would be used to characterize the scanner initially, and eventually would be modified to monitor defectivity in production. Similar procedures are found in other process modules; for example, a PECVD reactor running low-k processes may be qualified using a silicon dioxide process, since a standard process is needed to check tool health.
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| Materials, hardware and process parameters affecting immersion defectivity. |
A key parameter for i-litho defectivity is the speed at which the showerhead is moving over the wafer and the amount of water that is left behind by the trailing edge of the meniscus. These major sources of defects need to be understood as a function of the contact angle of the material exposed to water. Minimizing the amount of water escaping the trailing edge of the shower head and understanding the interaction of residual water with the photo acid generator (PAG) and quencher in the resist are key to faster ramp and qualification of i-litho cluster. This interaction of the material, showerhead design and exposure process parameters is a typical example of how immersion lithography has affected defectivity.
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| Typical examples of immersion-specific defect classes.1
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Blanket film defect signatures
Litho cluster qualification has traditionally relied on blanket wafer particle measurements, and such measurements will continue to be an essential part of the i-litho cluster qualification procedure. In addition, the ability to partition the defects using defect source analysis (DSA) has become critical, so that engineers can understand which defects arise from the immersion process during exposure and developer steps, vs. bare silicon, bottom antireflective coating (BARC), resist and topcoat coating processes.
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| Defect source analysis (DSA) methodology superimposes multiple layers of defects, and tracks the defect source back into the prior process steps. DSA can filter non-immersion-specific defects out.2 |
In addition, new advanced particle measurement tools enable an essential part of the litho cluster qualification: to characterize the interaction of the water, scanner and material on a blanket wafer to see what defect signatures emerge due to the introduction of water. The signatures will be a function of resist/topcoat stack, stage design, and showerhead parameters, as well as exposure parameters such as field size, scan speed, etc. If used properly, this characterization can be a very effective way to quickly identify and reduce patterned wafer defectivity, leading to faster ramp and qualification of the i-litho cluster.
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| Process effects detected by SURFImage and correlated to patterned wafer defects.3 |
Wafer edge defectivity
As an effect of immersion technology adoption and shrinking design rules, the real estate on the wafer is becoming increasingly valuable. The wafer edge is the last frontier where valuable real estate may be wasted — typically, manufacturers specify a 3 mm edge exclusion. Optimization of the edge bead removal (EBR) process has created an additional degree of complexity to the immersion scanner qualification process. EBR has traditionally not been affected by scanner parameters. However, with the advent of immersion lithography and with water going over the wafer edge, even previously ignored residue on the edge of the wafer has become meaningful. These tiny amounts of residue can be transported by the water as it goes over the wafer edge, and deposited on the rest of the wafer, leading to increased patterned wafer defectivity. Adhesion of the resist stack (BARC/resist/topcoat) at the edge of the wafer is another key factor; as the water goes over the edge, its force can cause delamination at the edge and result in flakes that get transported to the wafer center. As a result, the EBR process needs to be optimized as a function of the exposure process also, considering scan speed, stage design, showerhead parameters, etc.
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| Showerhead movement across wafer edge and resulting flake formation.4
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Overlay error and CD variation
The qualification goal for i-litho-induced overlay error is tool performance and stability that is equivalent to or better than traditional results using dry lithography. Increased overlay errors due to thermal stress effects associated with wet processing, first-wafer effects, edge-of-wafer effects and air turbulence necessitate the characterization and minimization of overlay errors as a function of immersion scanner parameters. Overlay error characterization will continue to be an important part of the i-litho cluster qualification.
Another area of continued focus for i-litho cluster qualification is CD variation. Measurement of CD variation may require over-sampling the CD across the wafer to fully characterize immersion-specific within-wafer and within-field fingerprints.
Conclusion
In the next six to nine months, immersion scanners will begin their phased introduction into manufacturing. A follow-up step — which may be even more important than the i-litho cluster qualification — will be to institute new production monitoring schemes for patterned wafer defectivity, blanket wafer process signatures, and edge bead removal for the immersion process. Changes to metrology monitoring procedures are also likely as immersion lithography moves into production.
- S. Nag and I. Malik, “Defectivity Challenges in Immersion Lithography for Sub-90 nm Technologies,” Interface Microlithography Symposium, 2005.
- K. Nakano, S. Owa, I. Malik, T. Yamamoto and S. Nag, “Analysis and Improvement of Defectivity in Immersion Lithography,” Proc. SPIE, 2006, Vol. 6154.
- F. Holsteyns et al., “The Use of Unpatterned Wafer Inspection for Immersion Lithography Studies,” Proc. SPIE, 2006, Vol. 6152.
- I. Pollentier, “Status on Immersion Lithography Processing,” IEEE Santa Clara Valley Electron Devices Society (SCV EDS) Meeting, Feb. 21, 2006.
