Sierra and Mentor Collaborate on Litho-Friendly Design
Laura Peters, Senior Editor -- Semiconductor International, 8/1/2006
Sierra Design Automation Inc. (Santa Clara, Calif.) is teaming up with Mentor Graphics (San Jose) to bring lithography data into the design phase, with plans to address process and lithography variations in an IC implementation design flow targeted at 65 and 45 nm designs. Sierra also recently unveiled Olympus-SoC, an IC implementation system that it claims bridges the gap between design and manufacturing environments. Olympus-SoC is a next-generation netlist-to-GDSII system that addresses lithography variation and timing closure in what Sierra said is the highest capacity IC implementation architecture in the industry. Olympus-SoC builds on Sierra's design for variability solution, Sierra Pinnacle, and extends it with litho-driven routing technology. Sierra said this new solution is targeted at high-end customers in wireless, handheld, graphics, set-top boxes, networking, and processor application segments that are designing at 65 nm and below processes. Olympus-SoC is currently in controlled availability at early partner sites, with general availability planned for later this year.
Under the announced Mentor collaboration, Sierra's Olympus-SoC will interact with Mentor's Calibre Litho-Friendly Design (LFD) to obtain the database of lithography hot spots and litho-unfriendly structures, then change the design layout to fix these errors. Mentor and Sierra said they would also work together to develop next-generation routing rules.
"We are excited to work with Sierra Design Automation and its variability-aware implementation system because it is an ideal platform to take advantage of this analysis to make timing-driven layout modification trade-offs at earlier stages of the design flow to dramatically improve layout robustness across process windows," said Joe Sawicki, vice president and general manager for the design to silicon division at Mentor Graphics, in a statement.
"Current techniques for litho hot spot removal make modifications to the layout without taking into consideration critical design metrics such as timing performance and OCV-related hold violations," added Pravin Madhani, Sierra Design Automation's CEO and president, in the statement. "Sierra's variability-aware IC implementation system can model the errors identified by the Calibre LFD simulations and can modify the design layout while ensuring timing closure."
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