New Approaches to Fabricating Metal Gates

The trend in advanced gate stack technology is clearly far from the traditional approach of a gate electrode of heavily doped polysilicon on top of a gate dielectric made of silicon dioxide or silicon oxynitride (SiON). Although these materials are fabrication-friendly, much better performance in terms of improved transistor speed and reduced current leakage can be obtained by switching to a metal gate and a high-k gate dielectric.

One approach to fabricating a metal gate is called FUSI (pronounced "foo-see," short for fully silicided gate), which is basically an extension of existing processes. The FUSI gate is regarded as a promising transition between current polysilicon gate electrodes and future dual work function metal gates that require new materials and more complicated processing. Silicides are already used on top of the source/drain and gate to improve resistance and provide a better interface between the silicon and vias that connect the transistor to the first level of metal interconnect (these vias are still typically tungsten).

Silicides are formed by depositing a metal, such as titanium, nickel or cobalt, on top of the silicon, followed by a thermal step (typically rapid thermal processing [RTP]) to create a silicide, such as TiSi₂ or CoSi₂. In the FUSI approach, this step is simply continued until all of the gate silicon is converted to a silicide.

At the VLSI Symposium, held in Hawaii in June, IMEC (Leuven, Belgium) reported several breakthroughs on nickel-based FUSI, describing it as a manufacturable and reliable process for the 45 nm node, with excellent low-power, high-performance specifications. IMEC researchers said they had improved the process window and also found a way to modulate the work function of the metal in a practical way.

A ring oscillator using low-power CMOS transistors with nickel-based FUSI gates on HfSiON achieved a record unloaded delay of 17 psec at an I_off of 20 pA/µm and V_dd of 1.1 V. The use of metal gates realized with FUSI process enabled further gate length reduction to 7 nm for NMOS and 14 nm for PMOS over polysilicon/SiON. In addition, IMEC demonstrated that metal gate on HfSiON devices can outperform optimized conventional polysilicon/SiON 65 nm devices by up to 25%.

By using a novel sacrificial SiGe cap at gate level, the process window, manufacturability and reliability have been improved. In a standard flow, polysilicon and spacer heights are not well controlled before FUSI because of non-uniformity in the chemical mechanical polishing (CMP) process and the need for overetch at oxide etch-back. The SiGe cap is deposited on the polysilicon film to absorb the process variability, resulting in an opening of the process window from ~5°C to ~20°C, meeting manufacturing requirements. For a 10-year lifetime, operating voltages of up to 1 V were extrapolated for NMOS and up to 1.2 V for PMOS devices with controlled NiSi and Ni₃₁Si₁₂ or Ni₂Si FUSI gates making it a reliable process.

To modulate the work function, IMEC developed a method to incorporate ytterbium (Yb) into the gate, which enables modulation of the V_t for nFETs. The ytterbium is predoped into polysilicon through ion implantation. The V_t of pFETs is reduced using a platinum alloy into Ni₂Si FUSI and by applying a strained Si_0.8Ge_0.2 channel. V_t's down to 0.25 V for nFET (NiSi:Yb) and pFET (Ni₂Si:Pt+SiGe channel) were achieved on SiON without degradation of the dielectric integrity and long channel mobility.

To eliminate the gate depletion effect and enhance transistor performance, metal gates are being introduced as a replacement of conventional polysilicon gates. Nickel-based FUSI has received growing attention for sub-45 nm CMOS applications since it eliminates poly depletion, is compatible with high-k dielectrics, is a known material in the industry, and can be integrated in a conventional CMOS flow.

Researchers from Taiwan-based UMC also reported success with FUSI gate technology at the VLSI Technology Symposium, describing for the first time a unique strain engineering technique used to enhance performance on FUSI NiSi gates. By simply reversing the sequence of two steps in the normal FUSI process, a unique "enveloped FUSI" scheme that results in a 10% drive current enhancement in NMOS was proposed.

An alternative to FUSI is to directly deposit metals with the desired work function. Work at Sematech , also presented at the conference, demonstrated progress in that area. "We developed an understanding of how metal electrode materials and high-k dielectrics react, and how the effective work function of metal electrodes can be controlled to yield an effective work function close to that of doped polysilicon gates," said Byoung Hun Lee, manager of Sematech's advanced gate stack program. "Our approach will enable the industry to implement metal electrodes with minimum modifications to current CMOS flow."

Sematech researchers described a new process that uses two different high-k films — if needed — and dual metal electrodes for nMOSFETs and pMOSFETs, respectively. This allows nMOSFETs and pMOSFETs to be optimized independently, thus avoiding the deleterious intermixing of gate stack materials that typically degrade V_t and other performance characteristics.

Called the dual metal gate (DHDMG) process, the approach is also more controllable, resulting in better-defined gate profiles. Ultimately, the process is relatively easy to implement, without the need for additional critical lithography levels or any significant increase in the number of steps.

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