Chip-Package Codesign Efforts Continue

Efforts to enable and advocate chip-package codesign have been underway for years. True concurrent design of chip and package started to become a reality as 90 nm process technology was going into full production.¹ One sign that it is becoming more than a trend is that two companies specializing in this area, Optimal (San Jose) and Rio Design Automation (Santa Clara, Calif.), recently announced a joint development effort.

Much of the work needed to create the necessary framework for codesign was done for the 90 nm node. Both companies currently provide tools designed to work with existing tools from the bigger EDA companies. The main drive of this joint development project was to enable concurrency for both design processes to be in parallel from the start.

The project linked Rio Design Automation's RioMagic product with Optimal's PakSi-E product. The announcement came only a week after Optimal announced a suite of products for system-in-package (SiP) analysis.

RioMagic is described as package-aware chip design software that performs interconnect synthesis from chip I/O to package ball. PakSi-E performs a three-dimensional electromagnetic analysis on the initial package design to verify it or identify possible changes. One of the goals is to settle on a chip I/O layout early in the chip design process that optimizes cost and performance for the overall chip-package interconnect system.

This may not seem to be much of an accomplishment, but it is. Since a package for a system-on-a-chip (SoC) may have several layers, and that package costs more than the die, optimizing the package design is very important. If an optimized I/O (signal, power and ground) layout on the die can eliminate one layer in the package substrate, then the optimization is an accomplishment of great value in terms of cost reduction.

Optimizing the chip I/Os from the start not only shortens time to market, it can lead to an optimized overall interconnect design.

If such a layout can be identified near the beginning of the chip design process, then the package design can be performed in parallel with the chip design, reducing product cycle time. Given that a package design for an SoC can take four to six weeks, the cycle time reduction can be significant.

If an optimized I/O layout leads instead to a more reliable or higher-performing package, it is still valuable. With IC clock speeds well into the gigahertz range, ensuring reliable package performance is a considerable task. At these clock speeds, any analysis of package performance — even a preliminary one — must include a thorough examination of electromagnetics. Putting this off until after the chip is designed would only ensure a delay to market.

A tool such as this could be useful for either an SoC or SiP product design. It could also be useful in making the choice between an SoC and SiP, since this is a choice that needs to be made early in the design process.

If an SiP approach is chosen, then concurrent design is essential. The package connects the die to each other in this case, and those package interconnects function the same as some of the on-chip interconnects for an SoC. These interconnects can also be implemented in different ways. In some SiPs, they would be traces in a substrate layer. Stacked-die SiPs use wire bonds to connect die to each other, as well as to the package. At the very least, the design of each die in a SiP needs to account for package interconnects from the beginning.

The companies plan to make more announcements over the next several months, and much more will be needed. The number of ICs that have thousands of I/Os will continue to grow. Forward-looking technologies like 3-D ICs and modules with die embedded along with passives may require something more than concurrent design to be viable.

The industry is in the process of taking the first step with regard to chip-package codesign: knowing that it is needed and making tools for it. More steps need to be taken to handle more complex chip-package designs, and design capabilities that do not yet exist will have to emerge and become established.