Nanotech Bolsters Semiconductor Manufacturing — Gradually

Paradoxically, in an industry that thrives on advanced technology, "change" is a pestilential concept to be avoided at all costs. Only when the semiconductor engineer finds that further workarounds are impossible, and that only a major alteration will allow passage into the next design node, will what today is termed a "disruptive technology" (a.k.a. change) be allowed. This seems particularly true of the introduction of nanotechnology into semiconductor manufacturing.
 
"The semiconductor industry is thinking beyond CMOS, but did not act on finding alternatives until recently," observed Ahmed Busnaina, director of the NSF Nanoscale Science and Engineering Center for High-rate Nanomanufacturing and the NSF Center for Microcontamination Control, at Northeastern University (Boston). "A group within SIA led by IBM, TI, Intel, Micron, AMD and Freescale, jointly with NSF, has funded nanoelectronics research projects at academic institutions last year through the new Nanoelectronics Research Initiative launched by the SIA. They're also funding two new centers, with a third one to be announced. One of the new centers is at UCLA and the other at Albany."

Most semiconductor companies plan on using carbon nanotubes as transistors and have modest goals. This research may advance current technology to 2020, but probably not beyond. Unsurprising, since our industry rarely looks beyond 10 years into the future — even the ITRS stops at 2020. Beyond lies unexplored territory and uncertainty as to what will be used (i.e., nanotubes, III-Vs, silicon nanowires). The ITRS, however, sets aside a section (emerging research devices) to address new technologies that cover CMOS-based and beyond, but sets no clear path as to where the technology is going. Some companies are considering silicon nanowires instead of nanotubes. Unlike carbon nanotubes placed on or grown normal to a silicon surface, silicon nanowires chemically grow along it and can be assembled in patterns on the surface. If tiny enough, they can be used to make minute transistors.

Unsolved problems abound. As shrinks progress, the CMOS transistor approach — charge-based electronics — makes it impossible to efficiently cool operating devices. Non-charge-based electronics are being considered. Nantero uses carbon nanotube-based mechanical switches employing mechanical positioning to store information. They are turned on and off by a charge, but the mechanical position holds the data. Samsung and others have produced mechanical switches that use carbon nanotubes arising like columns from a substrate, with an electrode drive to bring them together or pull one away to disconnect. There is a Japanese electromechanical silver sulfide switch that passes current, creating a chemical reaction resulting in a bump that makes or breaks contact. Not everything is electromechanical; Hewlett-Packard has a molecular electronics switch that also uses a charge to activate a switch.

Since nobody knows which technique will succeed, the industry keeps a wary eye on nanoscale science and engineering centers to see what kinds of novel switches might arise as transistor alternatives, how reliable they are, their manufacturability requirements, cost, scalability, thermal characteristics and availability. While CMOS has a breath of life left, semiconductor nanotechnology will get nowhere. So long as device makers can push down the scaling, costly new technologies will be avoided. Nanotech can help if, for example, specific materials such as composites are necessary.

Lithography is another question mark. Currently, pilot fabrication is conducted using extreme ultraviolet (EUV) lithography at ~30 nm. EUV can theoretically take features down to ~14 nm. However, it is unclear what will be used beyond 14 nm. Will strained interfaces or self-assembly be used to create small structures? These techniques, however, result in regular structures (uniform lines, dots, etc.), not irregular ones, necessary when designing a circuit. Nanotech offers few solutions at this time, especially since the semiconductor industry's funding is relatively small. This is why few of the nanotech centers are entirely devoted to nanoelectronics. Even so, current industry-funded centers are working on CMOS technology and its extension; not on its replacement.

Arguably, our industry is no stranger to nanotech, having operated at the <100 nm range in production for some time, but it is not as simple as that. As James Ryan, vice president of technology at the College of Nanoscale Science and Engineering of the University at Albany (Albany, N.Y.), indicated, "While there are complexities associated with implementing disruptive technology, nanotechnology is already being applied in the nanoelectronics industry, even as it continues to evolve. Extensive research and development is needed prior to full implementation to ensure that such technologies can be manufactured with high yield and reliability."

Nanotech advances are impelled by challenges — <100 nm wires that show noticeable increases in resistivity over bulk require improved materials, better processing comprehension, and increased defect control. Issues arise from making things so small, which require new metrology. Then there is the overall problem of fabricating smaller features, which drives patterning tooling along with the remarkable precision needed for etch and subsequent processing and surface perfection control.

According to Ryan, this evolutionary path probably will continue until 22 nm, which is where everybody today looks beyond conventional approaches. "IBM, AMD, TI, Micron Technology, Intel and Freescale are funding the Nanotechnology Research Initiative to research device areas beyond CMOS. The focus is on R&D for advanced non-CMOS devices and their fabrication. We're working on novel computing state variable devices and fabrication methodologies," he said.

The reality is that there has been a gradual implementation of nanotech that intersects just about every science. For instance, a common nanotech application is in paint for nanoparticle fillers. This is transferable to low-k research in new materials development to produce structural elements. Beyond this, work is required to learn how to control multi-phased materials and use them to generate patterns and devices, whether something "simple," such as porous dielectrics, or materials that can be spun on to the substrate to create patterns in a self-assembled manner.

Revisiting Moore's Law

Marc van Rossun, strategic coordinator of nanotechnology at IMEC (Leuven, Belgium), sees two nanotechnology domains. "One is the top-down approach, the other the bottom-up approach." Top-down is a familiar miniaturization approach. It is optical lithography, e-beam lithography, X-ray lithography and etch techniques. These are well developed, and their future simpler to extrapolate. The other domain, bottom-up, undergoing R&D, deals with atom and molecule assembly, and its progress path is unclear. Top-down is approaching the end of the road. Beyond the 22 nm node, it is unclear how much progress can be made toward further shrinks.

All this forces a redefinition of Moore's Law, shifting its focus from complexity and doubling the number of transistors to increasing circuit functionality. Even the ITRS will have to branch out; some parts will diverge depending, for example, on acceptable power dissipation levels. Heterogeneous integration will be another consideration — hybrid chips with non-logic functionalities. An important paradigm shift is that from single- to multi-core architecture; as it pertains to data handling, complexity alone is no longer the chip's potential determinant.

Although there is a good understanding of material characterization basics, we lack sufficient control at the nanometer scale. Increasingly, materials' properties must be mastered by controlling their shape at extremely small scales. This holds true for things like high- and low-k materials as well as, under different circumstances, gate materials. Materials interactions are growing complicated in processing, characterization and modeling.

Since some aspects cannot be directly observed, modeling algorithms tend to drift from reality. Increasingly, there are more intermediate layers between what are modeled and observable parameters. Once, semi-empirical models with simple measurable parameters traceable to the model were sufficient. There is now a material optimization bottleneck, because there are not sufficient closed feedback loops between measurement and modeling.

And the kitchen sink

Lucent Technologies (Murray Hill, N.J.) sees higher integration for greater functionality as a strong trend for nanotech. According to Don Tennant, distinguished member of technical staff, they have projects to integrate large mirror arrays with ICs and develop ways of packaging them together. "We don't push the IC per se, " Tennant said. "Sometimes we use relaxed line rules. The value comes from coupling sensors or mirror arrays and other MEMS devices to produce packaged systems. Instead of an ASIC, we get an ASIS (application-specific integrated system) — a system-on-a-chip. If you view nanotechnology as including things like sensors and MEMS devices, this is doable now."

This rapid progress is possible because traditional IC fabrication toolsets, manufacturing capability and know-how are applicable to much of the work. Just as one transistor is uninteresting, yet millions enable a powerful circuit such as a microprocessor, some of Lucent's projects involve not one mirror, but massive mirror arrays (Fig. 1 ). Texas Instruments' HDTV mirror array chip, an IC with integrated MEMS, revolutionized consumer electronics. An even denser spatial light modulator is being developed via a DARPA project, which involves an integrated optical MEMS chip for maskless optical lithography. This too could prove revolutionary by replacing the photomask with a programmable mirror array. While the predicted low throughput of such a system may preclude its use for mass production of logic and memory chips, it is an attractive alternative for ASIC applications, prototyping, or for sensitive military applications where the design does not go to mask shops.

1. Prototype MEMS mirror array chips developed as part of a DARPA-funded research program on optical maskless lithography. The piston-type mirrors ride on the sinusoidal springs visible beneath, and are controlled by individual electrostatic actuators under the springs. A higher fill-factor version chip is shown in the inset, with a single mirror pulled down. (Source: Lucent Technologies, Bell Labs and DARPA)

We are reaching a level where linear increases in performance complicate matters and margins are shrinking. Still, engineers will improve circuit architecture before trying to boost performance. Predictions that CMOS will run out of steam within a decade are subject to the definition of "running out of steam." Some applications do not require 90 nm node technology; 130 nm or even 180 nm can still be used when it is more cost-effective and provides better margins in parameters like thermal budgets and current drive. Yet the resulting chip-sized system will be state-of-the-art because it incorporates additional functionality.

By 2016, circuits will not appear very different; they will still rely on CMOS technology, possibly with patches of other materials and the actual active switching area going from silicon to perhaps carbon. However, the basic substrate, interconnects, capacitors, all the three-dimensional buildup of the IC will not abandon silicon technology.

Using what is available

Mainstream companies like Applied Materials (San Jose) view themselves as already being in the nanotech zone (Fig. 2 ). "If you consider nanotech as based on dimension or fabrication method — whether top-down or bottom-up — we're exploiting nanotechnology's properties and benefits while trying to overcome challenges associated with small sizes and continue CMOS growth," said Nety Krishna, director of advanced technology.

2. Advanced ICs are nanotechnology. Ever since going below the 100 nm level, the semiconductor industry has been working at nanoscales. However, nanotechnology as represented by materials beyond CMOS, such as carbon nanotubes, is still far into the future. (Source: Applied Materials)

Here, nanotechnology is used for functionality and performance. The gate stack with self-assembled nitrogen in the gate dielectric (SiON) is an example. Device makers deal with some 10 nitrogen atom layers in the gate dielectric. How the nitrogen is added is critical to a dielectric's performance, as well as how it remains and provides the correct current, threshold voltages and leakage.

Another is ultrashallow junction, where both junction depth and abruptness, of which the latter is now only a few nanometers, are controlled with ~120 nm of junction depth at the 45 nm node. How the source, extensions and implants from 10 to 30 Å are controlled is critical; they must be deliberately engineered. Another example is strained channels where selective epi (SiGe) is grown, demonstrated by Intel for the 90 nm node. Applied is pursuing this for 65 nm and attempting to evolve it to future nodes. This will require additional layers on top to continue to boost performance. A 0.01 level change in the lattice parameter can result in a 50-100% performance boost in drive currents.

There are three broad categories to consider. The first is channel engineering, where more must be done to maintain the gains obtained with strain. A possible disruptive technique might be germanium, either in the channel or as the channel itself. However, the quantities would be so small that they would have to be controlled at that level, which is a key nanotech problem.

The second is interface engineering. The industry has progressed from thick to thin films. Now there are only interfaces, and these drive performance. Interface engineering will be extremely important for gate stack, interconnect and packaging. Wet chemistries may become more significant in how they help overcome interface-engineering issues.

The third category is broad: novel materials. Specifically, films engineered to affect photoresist, low-k, non-volatile memory technologies, porous low-k, and packaging. Novel thinking is required for how polysilicon is dealt with in the area of traditional non-volatile memory. Grains are so small that some gates have one grain and others two, causing variations. When designs move to charge-trap devices, the silicon nitride put down for the charge-trapping material will be silicon nitride in name only; the film generated will be different because of the distribution of bulk traps, where the surface traps go, and the engineering of bulk traps so that they remain in the bulk for hold and electrons. CMOS' future is linked to nanoengineered materials.

Lithography and nanometrology

Advances such as step-and-flash imprint lithography, being worked on by Molecular Imprints (Austin, Texas), will enable nanoscale technology in manufacturing in the <50 nm domain. In the fundamental patterning area, the capability of creating features down to 25 nm has been demonstrated in printing and etching. The current capability to create nanoscale patterns makes it possible to work in the photonic, magnetic data storage, and biotechnology space. For example, if constructs a tenth the wavelength of visible light are possible, structures that allow photons to be manipulated can result. Although advanced, this technology still requires further development for CMOS.

Linewidth is certainly a primary metrology driver. "As we progress across the nodes, resolution requirements are increasing (Fig. 3 ). Thus, tools have transitioned from optical-based to SEM to S/TEM to ultimately TEM tools. This will continue," said Matt Harris, vice president of worldwide marketing and business development at FEI (Hillsboro, Ore.). Another major driver is complexity. As chips become multilayered and features increase in complexity (more three-dimensional), additional cross-sectional analysis is needed; features must be viewed sideways as well. Cross-sectional views, coupled to top-down views and stacked over multiple cross-sections, can give a good 3-D analysis of a finFET, for example, where it is important to look for gate thickness, depth and layer thickness.

3. At <65 nm, 50% of key applications will transition into the S/TEM space. R&D, development and ramp will require three-dimensional subsurface metrology. (Source: FEI)

As linewidths have decreased, lithography's journey has not been easy, and it is increasingly difficult for lithography to travel down the dimensional curve. "It stalled at 193 for awhile," said Lance Glasser, CTO at KLA-Tencor (San Jose), "so engineers substituted with new materials and new structures or device architectures."

This generates a series of hurdles because new materials intersect and interact in unexpected ways, their integration is difficult and, of course, each must be measured and their properties determined. So metrology needs arise not just because things are smaller, but because 3-D has grown in importance and new materials are present.

We cannot afford to have too short a horizon in electronics. Nanotech should not be undervalued because it does not improve the transistor in the short term. It is a long-term implementation, but most certainly the new applications and businesses that will be created because of it will be inextricably linked to silicon in both traditional and unexpected ways. Many of today's monolithic industries, firmly tied to silicon, will become more diverse and applications-nimble.

The best is yet to come.