Steven Hillenius, Vice President, Semiconductor Research Corp.

Steven Hillenius (Source: Semiconductor Research Corp.)

Steven Hillenius is vice president of the Semiconductor Research Corp . (SRC, Research Triangle Park, N.C.). Before SRC, he headed technology development and collaborative interactions for Agere Systems and Bell Laboratories. His team at Bell Labs was the first to produce 60 nm transistors, and they conducted much of the early materials innovation on high-k gate dielectrics and novel three-dimensional device structures. He managed partnerships and joint-development programs with NEC, STMicroelectronics, TSMC and Chartered Semiconductor. Hillenius is an IEEE Fellow, past president of the IEEE Electron Devices Society, and a board member of the IEEE. He holds eight patents that resulted from his device and process research, and has published more than 60 technical papers. Hillenius received a B.S. in physics from the University of Delaware in 1973 and a Ph.D. in physics from the University of Virginia in 1979. SRC is a semiconductor and related technologies university research consortium, composed of 23 companies and partners and 100 universities worldwide.

SI: As the holder of a number of patents in the field, how do you view the present direction of device technology?

Hillenius: From my 25-year experience in the industry, the thrust has always been on scaling transistor dimensions — Moore's Law-driven activities. This is still true today; however, as device scaling gets increasingly difficult, some unexpected aspects begin to gain in importance. Scaling features has improved transistor performance and cost-effectiveness because of the extra functionality packed onto the silicon. Then physics began getting in the way, and while individual transistors used less power, the chips went the other way and the focus had to shift to lower-power devices that weren't as fast, particularly as applications grew more consumer-oriented. This kind of activity, where we go down a certain path and discover that there are other pieces that must be fixed before continuing, is sure to go on, because it's been the natural progression of the semiconductor R&D for the last quarter century.

SI: Is current R&D effort correctly oriented?

Hillenius: You never know, at any time, whether you're doing all the right things. The R&D engine and manufacturing direction of the industry responds quickly to change to correct problems and defy predictions. According to the ITRS's high-k projection requirements of five years ago, by now the standard CMOS device should have a different gate dielectric than SiO₂ — a high-k material. It turned out that high-k materials are difficult to incorporate into device structures, and the fears for the inability of SiO₂ to be a good gate insulator turned out to be premature.

SI: So, any solution to avoid change?

Hillenius: Certainly. We avoided having to incorporate a new material by designing around the leakage in the thin gate dielectric using SiO₂ . It's that kind of real-time solution to the unanticipated results of the research that we see continuously. In general, as manufacturing gets increasingly expensive, as device physical limitations get more difficult to overcome, and the ICs themselves become considerably more complicated, the solutions that come out tend to be along the lines of better modeling, better design, and design architectures that work around the shortcomings of other solutions we've been unable to achieve. In the case of power, a solution to this is to design for power-down cycles, different ways of powering up parts of the chip, and just more efficient processing algorithms. Wherever the research has the biggest value-add for the whole system, it'll be adopted. Currently, systems design, circuit design, and the systems architecture are really where the significant improvements originate. The centroid of the true development is moving further away from device improvement and more toward the design and systems — both tools and algorithms.

SI: You mentioned Moore's Law. How do you achieve a balance between scaling and functionality?

Hillenius: (Smiling) From a transistor-level perspective, you cannot make a device that's smaller than an atom. I think we'll still see transistors functioning at the 10 nm feature size range; whether or not those devices will have better functionality than something slightly larger will depend on the application. Already for scaled devices in digital logic you find that you must back off from ultimate shrinks for the system's analog components. The tiniest devices, the ultimate devices, will be used for certain functions, but there will be many other devices that aren't pushing the limits of either physics or feature size doing many of the other functions. There will be a leveling off of the highly integrated functions with multiple technologies and devices on either a single chip or a system-on-a-chip or package. Will 10 nm transistor be the dominant device for large digital chips? Most likely not — it'll be a mixture of things. Even now, the smallest devices run at a volt or less, which is difficult to interface to the outside world; thus, ICs made today frequently have two or three power supply voltages — the I/Os are higher voltage. This will continue.

SI: So-called conventional wisdom indicates that, at 45 nm or so, CMOS will begin to run out of workarounds. What is your view?

Hillenius: There will always be workarounds regardless of the architecture level. The real question is where do diminishing returns make it worthless to attempt those smallest devices if additional design is needed to make up for shortcomings in most of the applications?

SI: It appears at present that clock speeds can be increased far beyond what they are today; multi-core microprocessors seem to be a stopgap measure. How can we get around that problem?

Hillenius: If we just consider real high-speed applications, multiple-core designs will continue, especially as CAD and other design tool architectures improve and become more compatible with these architectures. Multiple-core may replace single-core at high speeds, because the problem is not just a matter of clock speed, but of distributing the clock across a large chip. With multiple cores and multiple clocks, the matter is resolved as long as it is possible to create an architecture that allows the distribution of functions in such a way that is faster and more efficient in collecting the data. This is a technical solution that gets around the need to have an increasingly faster clock over an increasingly larger area.

SI: What is the status of EDA, particularly the modeling area, where algorithms seem to slowly be drifting away from reality as they must cope with things like transistor parameters shifting as a function of time, providing performance at the transistor and interconnect levels, power dissipation, speed performance, etc.?

Hillenius: Here is the meat of most of the real development that will take place. Nothing prevents us from modeling these features; they are predictable. It's just a matter of getting the compact models into place, the practical issues of being able to use those models in real-time design. That'll be a growth area in the development world, especially with wafers and design getting so expensive, making modeling cheap regardless of its price if the tools are accurate. The development of these tools must be a high priority for the industry.

SI: Any thoughts on immersion lithography developments?

Hillenius: The big gating item for any tool is if you have to retool everything to go on — a huge development expense. Immersion lithography allows you to use the source, optics and other factors with just a modification to the stage and wafer environment. It's still a tall order, but far easier than shifting over to a new wavelength or to something like electron beam. There's no question, in view of how far things have come, that immersion lithography will be the thing for 45 nm and below. It pushes other radical changes at least another node down the road.

SI: How do you see the progress in circuit hybridization, as in the case of nanotube applications?

Hillenius: Pulling together multiple technologies — even III-Vs — on CMOS is definitely a growth area. As design and manufacture for digital and even mixed-signal CMOS becomes increasingly standardized and cheaper, the value-add for applications will come from integrating other things to the silicon, such as sensors, or higher-voltage activity being hybridized in a variety of ways. Some of it might be on-chip with different materials, some of it will be a system-in-a-package, some stacked-chip applications. We're seeing some of this now. Clearly, this is a straightforward way to integrate more function into a small area.

SI: When will nanotech become mainstream?

Hillenius: (Laughing) That's something that I wouldn't even hazard a guess about! When you look at things like nanotube development, research on all possible applications — most way beyond electronics — I can see these being integrated on silicon for a particular function that cannot be done in any other way. However, I don't see it taking place right now; it's too early. If I had to provide a timeframe now, in view of the technology's maturity level, I don't see it as being in full-scale production in things like cell phones or body sensors for another decade. Although there isn't a major application in electronics for nanotechnology at present, it has all the ingredients of being a very disruptive kind of application. The raw material — carbon — is cheap, very much like silicon.

SI: What would you say is the most serious technical problem in semiconductor technology today?

Hillenius: Managing complexity. In the whole process from conception to the delivery of the IC, the biggest percentage of time is spent in design and verification. This is a symptom of a very complex problem that's growing far faster than our ability to track down each detail. It's this complexity that pushed verification tools to their limits and causes respins in either the design or the manufacture.

SI: R&D is getting more expensive. How can the industry cope with this?

Hillenius: When R&D gets too expensive for a business or industry to support it, a more inexpensive way to attain the desired results must be employed. This may sound like a cop-out, but it is the way business works. Just as in the case of keeping up with Moore's Law, workarounds must be devised. Here is where pre-competitive research proves its value, beginning at the development of solutions that the industry will require. Particularly in a field like semiconductors, research can only be supported by a market that grows fast enough and provides consumer demand for new applications. You must also be careful where you invest your R&D money. I remember in the early 1980s big companies like AT&T and Motorola projecting that, within that decade, silicon would be obsolete and gallium arsenide would be the thing. Back then, you could have started a several-billion-dollar crash program to produce 8-in. GaAs wafers to get to the next generation. Fortunately, the industry seems to be, most of the time, self-correcting.