Better Barriers for Copper

One of the main culprits in copper electromigration (EM) is often a weak interface between the copper line and overlying barrier dielectric. New self-aligned CuSiN processes have been developed to improve this interface. Researchers from the Crolles2 Alliance (Crolles, France) and NEC Electronics (Kanagawa, Japan) revealed results of their self-aligned CuSiN processes at the recent International Interconnect Technology Conference (IITC) in Burlingame, Calif., last month.

To maintain low effective dielectric constant in multilevel stacks, it is necessary to incorporate barrier layers with lower-k. The switch from SiN (k~7.0) to SiCN (k~4.9) has occurred in previous nodes, but a further migration to SiC barrier (k=3.5) initially led to reliability degradation. Tatsuya Usami and colleagues at NEC Electronics, together with engineers from Novellus Systems (San Jose), developed a self-aligned CuSiN process in order to realize a highly reliable interface with the SiC barrier. The new process involves three steps: a reducing plasma to convert copper oxide; silane gas exposure to diffuse silicon into the copper; and a nitrogen containing plasma to scavenge excess silicon and generate Si-N bonds. Next, plasma SiC was deposited using a complex organic methylsilane source.

The NEC researchers note that the CuSiN process is simpler than selective CoWP processes, which require an extra preclean and plating process. Also, there are leakage current concerns associated with CoWP selectivity loss. The test structure used consisted of a 90 nm node single damascene dual-layer structure with SiOC interlayer dielectric, oxide hard mask and SiCN dielectric barrier. The baseline SiCN was replaced with the self-aligned CuSiN process and low-k dielectric barrier (3.5) at the lower level. Minimum line/space were 0.12/0.12 µm with 0.12-0.15 µm vias.

The researchers performed via yield, line-to-line leakage, capacitance and sheet resistance tests in addition to EM and time-zero dielectric breakdown (TZDB) tests. The CuSiN process resulted in a 4% reduction of capacitance relative to the SiCN barrier. Via EM lifetime was 39× longer with the CuSiN process relative to the ammonia pretreatment, conducted at 300°C and 2 MA/cm². Dielectric breakdown testing showed 1.5× better TZDB (at 150°C) and a more controlled distribution relative to the ammonia baseline process. The improvement in EM performance is likely caused by reduced Cu-O bonding at the copper surface, shown by XPS. Also, a higher nitrogen:oxygen ratio was evident at the barrier dielectric interface, which helped breakdown strength.

Work headed by Laurent Gosset of Philips Semiconductors (Crolles, France), together with colleagues from STMicrolectronics, Freescale Semiconductor, Philips Research (Leuven, Belgium) and CEA/LETI (Grenoble, France), compared several ways of achieving self-aligned barrier integration using copper line surface treatments as well as selective deposition of metals (tungsten, CoWP, etc.) on top of copper lines.

The group investigated a three-step CuSiN process involving helium-based cleaning, copper silicidation using silicon-based precursor (silane, trimethylsilane), and NH₃ plasma to prevent further diffusion of silicon into the copper under thermal or electrical stress. This process (Figure ) was found to provide a better barrier to copper diffusion and oxidation. The researchers proposed that the mechanism may be caused by the formation of an ultrathin SiN film above the modified copper surface during the sequence. A key advantage to the process is its direct compatibility with existing PECVD processes and tools.

CuSiN/SiN bilayer simultaneous formation mechanisms during CuSiN process and the accompanying TEM cross-section. (Source: Philips Semiconductors Crolles R&D)

Gosset's group also investigated tungsten CVD, with the objective to completely replace the dielectric liner with a tungsten cap. The great challenge is selectivity loss, so a nitrogen plasma and pre- and post-deposition HF wet cleaning had to be introduced. Promising results in terms of leakage current, barrier efficiency against copper diffusion and oxidation were achieved.

Both palladium-catalized and palladium-free chemistries were investigated for cobalt-based self-aligned barriers (SABs). While other capping metals were developed (nickel in place of cobalt, rhenium or molybdenum in place of tungsten), cobalt-based SABs proved to be the most promising material from an integration standpoint. They determined that cobalt-based SABs are not efficient enough against copper diffusion without the additional dielectric barrier. Oxygen-based plasmas were found to damage SAB integrity. And, the via opening step must be optimized to either stop on the cobalt or completely remove it, without damaging the ultralow-k sidewalls or overetching the feature. Post-etch wet cleaning should avoid the use of water, which can induce cobalt/copper galvanic corrosion.

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