Improving Design Robustness With Via Doubling

Yield has always been an issue, but the degree to which nanometer technologies have created additional concern is unprecedented. In complex, high-performance designs, acceptable yield has been extremely difficult to attain and stabilize; yield levels have been dropping steadily with each new advancement of Moore's Law (Fig. 1 ). Everyone along the design and manufacturing flow knows the stakes are high, but just how does it affect the bottom line?

John Schmitz, vice president and chief operating officer of Sematech (Austin, Texas), stated in a recent presentation an estimate of manufacturing cost: a 1% yield loss in a 300 mm wafer fab will cost a chipmaker ~$5M on an annual basis.¹ No wonder yield is at the forefront of issues facing the semiconductor industry.

Dealing with the variables of yield loss requires multiple solutions from across the layout to silicon flow: design, manufacturing and test. Manufacturing and test have long been the arbiters of yield, and have extensive systems in place to help stem the slide toward less yield; without these systems, yield would not be possible at all. But in nanometer designs, extensive yield consideration must take place before the design goes to the manufacturer. That is why there has been so much emphasis on the design for manufacturing (DFM) movement.

Addressing yield loss in three areas

Yield loss can be categorized into three areas: random (usually particle defects), systematic (pattern dependencies in the layout) and parametric (timing-related issues). Designers, manufacturers and the EDA industry are working together to address solutions in each area. A number of solutions have been introduced, and others are in development. It is through testing and production that one technique in the designer's arsenal can improve yield in all three areas of yield loss. This is the fairly common design practice of via doubling.

1. Initial production yields have not improved, and mature yields have declined.

Here's why: Variation is part of the manufacturing process. Steps taken to reduce this variation are rewarded with improved yield. The number of single vias and the number of via transitions with minimal overlap can contribute significantly to yield loss. Placing a second via is a preemptive technique to reduce variation that occurs during manufacturing. By anticipating the "what ifs" that could arise, via doubling directly impacts all three areas of defects, thereby preventing loss before it happens in manufacturing.

Random defects are byproducts of the manufacturing process; for example, an airborne particle or, more likely, a particle that breaks off during polishing. If a particle lands on or near a single via, it can block the via from functioning. Inserting a second via is "insurance"; that is, the second via will perform if the one via is unable. The before and after effects of placing a second via can be easily measured with a critical area analysis tool, which allows the designer or yield engineer to assess the sensitivity of the layout to random particles. Through this one analysis, an estimate can quickly be made of the manufacturing payback of via doubling on random yield loss.

Systematic defects are a result of interaction between the layout patterns and process variations, such as antenna effects, planarity, via opens and electromigration, as well as chemical variations in materials. When copper was introduced in the manufacturing process, air bubbles became a problem because they have a tendency to accumulate at areas of stress, such as a via insertion point. The stress from the manufacturing process caused by the layout patterns can void a via. Placing a second via helps disperse the air bubbles and improve yield. Since layout configuration impacts the likelihood of a problem occurring, it is important to identify the layout patterns that will cause a systematic defect. This is where a powerful geometric processing engine can be used to notify users of potential problems.

Parametric defects center on timing, power and other functional requirements, and can have significant impact in nanometer designs. These defects are the result of interconnect parasitics and device physics. Single vias contribute to the problem: If a via becomes partially blocked, it produces a greater resistance (called a resistive via), and its performance is inhibited. By providing an alternative path, a second via reduces resistance and improves performance.

There is no doubt that doubling vias can improve yield. In fact, it is no longer a question of if vias should be doubled, but how. But inserting second vias is not without concern. One method is to double every via on the design. Given the statistical nature of via failures, in which a percentage of vias will fail, making a blanket rule to double every via is too high a penalty to absorb for most designs. An alternative approach is to double vias where possible without increasing the design area. This is referred to as taking advantage of "white space." This approach has proven very valuable because it balances the need to double vias and minimize area.

Another important issue is minimizing the parasitic impact of doubling vias. An advanced via doubling tool can analyze multiple via patterns that will maximize the coverage. Such a tool can then select the optimal configuration that orients the second via in the preferred direction (i.e., the direction of existing metal lines). This decreases the capacitive impacts caused by the additional metal.

Via doubling in the real world

What does via doubling do under actual foundry conditions, and what yield is possible? Recently, a chip on which via doubling was applied was manufactured by Chartered Semiconductor at the 130 nm process node. The chip was a coprocessing component used in handheld cell phones. The combination of good design practices and via doubling achieved an excellent initial yield rate above 90%. The exceptional results placed this chip in the initial yield scores previously enjoyed at 500 and 350 nm processes (Fig. 1 ). What does this mean for the design company who created the chip? A lot.

The handheld cell phone market is highly competitive and global, with new-generation models frequently produced and marketed. Cell phone makers, which are the customers of chip component makers, have to rely on the immediate availability of large numbers of components in order to make early prototyping of the newest products and create supply as the demand heats up. Having a high initial yield of the components needed in these products provides instant payback to the chipmaker: The customer has the parts for customers to use in a very competitive market. In addition, with an initial yield above 90%, there will be a faster ramp to yield stabilization, putting the chipmaker in an enviable "parts available" position when the cell phone maker calls for more components.

On the flip side, if the chipmaker cannot supply the demand — a situation that could easily arise if the initial yield is low — the cell phone producer would need to look elsewhere, since a reliable source of components is necessary to make the competitive market window of new phones. Unreliable chips put both chip and phone makers in jeopardy of losing revenue and profits. In addition, if semiconductor foundries push out delivery dates on chips, as recent announcements have stated, it results in longer delays. This can create a serious market situation if an initial yield is less than that required to fulfill a demand for a chip. It's what a McKinsey study calls "opportunity costs." This study shows that, on average, companies lose 33% of their after-tax profit when they ship products six months late.² This is a likely scenario if yield is low.

To examine the effectiveness of via doubling, an apples-to-apples test was conducted recently at an IDM. For this experiment, it was important for direct comparison that the design share the same wafers and the design size remain constant. The wafers were manufactured by alternating between die with single vias and die with doubled vias. In the doubled vias group, vias were added only where white space was available. Yield from both groups was tallied. The result from this single comparison was that the wafers manufactured with doubled vias provided a 6% increase in yield over the wafers with single vias.

Each company will have its own business model of determining loss of profit. But to figure how yield of a single chip can impact the bottom line, simply combine the manufacturing cost accounted for in the Schmitz yield loss calculation with the McKinsey opportunity cost calculation. Based on these results, management is likely to demand that via doubling be adopted in the design flow.

Which via doubling way is better?

The via doubling routines currently available from the EDA industry are run as a post-processing step to place and route (P&R). This is understandable, given the number of variables that a P&R system already has to balance, such as making correct connections in the smallest areas while trying to achieve timing. But differentiation with current solutions comes down to coverage and run time.

Coverage is directly influenced by the tool's ability to examine the layout and determine the best method for doubling vias; after all, layout, by its nature, is inconsistent. A powerful geometric processing engine is critical to this effort, because it can examine the various configurations and then select the best one that minimizes the timing impact. Run time is critical because via doubling occurs at the end of the design cycle when the schedules are always compressed. Again, a robust geometric processing engine is required to achieve via coverage in the shortest possible runtime.

DFM operations are gaining in importance, but are still relatively new. To be of value to the designer, DFM solutions need to be easy to use, able to be integrated into the design flow, and be capable of back annotating any change to the design database. The Calibre via doubling solution from Mentor Graphics provides a way to incorporate via doubling as a natural extension of the design flow. For instance, most P&R users employ multiple systems; Calibre's via doubling algorithm eliminates the design flow question because it can be used across multiple design environments. And because Calibre is fueled by a robust polygon-processing engine, it can manage back annotation, coverage issues, and meet runtime expectations (Fig. 2 ).

2. The Calibre via doubling tool identifies via transitions by layer and via count, presents via statistics, and determines layout quality. If requested by the user, the tool will perform automatic via insertion, adding metal in the preferred direction.

Technology will continue to advance, and so will the challenge of enhancing yield. While via doubling is an important part of improving yield, it is only part of the solution. To manage manufacturing variability, it is important that designers, manufacturers and the EDA industry work toward solutions that span across the spectrum of design, manufacturing and test. It is also important that the solutions that bring these disciplines together be easily integrated across respective environments.