Litho Simulation Enables the Leading Edge
Aaron Hand, Managing Editor -- Semiconductor International, 7/1/2006
|
When lithography simulation began to be explored more than 30 years ago, it was in an effort to turn optical lithography from an art into a science — away from the typical trial-and-error approach to process optimization.1 It became an idea whose time had come, despite the fact that the industry was still printing features that were several times larger than the wavelength of light being used. Today, as lithographers travel deeper and deeper into the subwavelength regime, it's an absolute essential. "Not a single IC is being built today that is an advanced IC where the line placement hasn't been controlled by somebody's simulation," noted Jim Wiley, senior technical director at Brion Technologies (Santa Clara, Calif.).
A key reason for the need for lithography simulation is sheer complexity. With hundreds of different variables in the process, no human could possibly comprehend the interaction between all the variables without some form of software package. "In the past, you could go through and just optimize discrete components of the food chain or supply chain and make a big jump," noted Bob Naber, product marketing director for RET products, DFM, at Cadence Design Systems Inc. (San Jose). "All the margins are so small now, that you can no longer get the big benefit from optimizing a single one. You need to optimize the interaction of all of them."
At the 45 nm node, features will be imaged at about a quarter the wavelength of the 193 nm light source used. Even the pitches are subresolution — 130-140 nm at the 45 nm node, noted Dinesh Bettadapur, president and CEO of ASML MaskTools (Santa Clara, Calif.). "This induces extreme proximity effects, which need to be comprehended as part of litho simulation. Also, these small features and tight pitches are being imaged using advanced scanners with ultrahigh NA, immersion, and likely some form of polarization as well," he said. "All the models used in a lithography process such as the resist model, OPC model and the imaging model have to comprehend these new effects and paradigms. If this is done well, it results in a good match between simulation results and wafer results, thereby enabling a very reliable and predictable process."
Ultimately, the reason to use lithography simulation software is to improve yields and ramp products faster. Simulation enables fewer reticle iterations, for example, noted Ed Charrier, vice president and general manager of the Process Analysis Division at KLA-Tencor Corp. (San Jose). "If it takes you two or three months from the time you tape out the design, print the reticle, run it in the fab, figure out something's wrong, and then respin it, if you can reduce it by one cycle to ramp a fab, it's as much as $1M a day that you're adding to the fab profitability — a lot of money."
Given a 300 mm foundry producing 40,000 wpm with a gross margin of 48%, even just a 1% increase in yield would equate to $58.2M per year, according to a report from VLSI Research. And with every generation, yields are ramping faster. Intel has shown a yield improvement for each process node, with the 65 nm generation reaching mature yield in less than two years. Advanced Micro Devices (AMD) has seen an 80% reduction in time to mature yield over the past three generations.2
Getting the necessary yields is the key component in an ever-shrinking time to market. "The time to market can be weeks, where you used to have many months or years to introduce a product and make your money," said Tracy Weed, director of the Manufacturing Enabling Products Group at Synopsys Inc. (Mountain View, Calif.). "With these consumer products, which is really driving a lot of what we do, if you don't get it in when the consumer wants it, you're not just losing market share, you might not have any at all. So that's really one of the places that simulation helps."
Changing face of simulation
Charrier, who has been working with KLA-Tencor's Prolith software for 12 years, has watched lithography simulation progress over time — from the early days when lithography engineers used simulators almost like a calculator, pulling out the software to answer a lithography problem, and getting a number to achieve better manufacturing and ramp processes faster.
Today, litho simulation finds use across the whole spectrum of the industry — from basic research straight through to final tapeout. Researchers may use simulation to understand the fundamental principles around lithography; models can indicate the applicability of a given resist or mask or illumination scheme, for example, long before any experiments are possible. Further down the road, litho process development engineers use simulation for process optimization, RET selection, and RET optimization, as well as sensitivity analysis. This category of use is typically done by desktop systems that take a close look at small clips in the design — perhaps as small as a single bit of a memory cell. This sector of the market has been led by KLA-Tencor (with its acquisition in 2000 of Finle and therefore Chris Mack's Prolith) and Sigma-C. Other players include ASML MaskTools, and the bigger IDMs typically have their own in-house tools.
Further down the food chain is full-chip correction of designs. Full-chip simulation operates on empirical or semi-empirical models to approximate the behavior of a physical system. These tools work at a much faster pace than the desktop simulators (a matter of hours for a full chip design), but take a hit in accuracy (typically 3-10×).1 This space is dominated by Mentor Graphics and Synopsys, with Brion Technologies also gaining recognition more recently.
And now simulation is not just needed by the litho engineers, but also as a way to communicate between the designers and the manufacturing fab, Charrier noted. A recent development has been in the realm of "litho-friendly design," which involves getting simulation tools into the hands of the designers — putting the capabilities further upstream to catch hot spots that may arise from manufacturing variability. "More recently, litho simulation software has also started to surface during the chip design process due to the increased focus and attention on DFM," Bettadapur said. "However, the litho simulation capability for designers is much more tailored to their specific needs, and takes into account the fact that chip designers are not lithographers."
In addition to the other big EDA companies, Mentor and Synopsys, Cadence has also entered this arena, partnering with ASML to offer MaskTools' LithoCruiser simulation in its Virtuoso RET suite. "What we're trying to do is take what in the past was a behavior set that was dominated by design-rule checking and rule-based checking in general, and we're trying to take this model-based simulation technology and push it upstream — as far upstream as we can, in the end, to try to head off all of the problems that tend to show up at the very end of the design stream right now," said Mark Miller, vice president of business development, DFM, at Cadence.
"The designers need to start paying attention to this stuff from the very beginning of this design flow," added David Thon, product marketing group director, DFM, at Cadence. "Not even just treat it with OPC at the end, but design it with OPC in mind at the beginning so that when you do get around to actually doing the treatment and printing, it's more likely to work; you get fewer surprises."
Synopsys is aiming its lithography compliance checking (LCC) at the design community to push knowledge of the lithography process up into the design as far as possible, Weed said. "You can basically apply this, and it will identify these hot spots, and you can fix them right away. So there's an automatic correction," he said. "A lot of tools that you'll see will identify these hot spots, but then you're left to your own to figure out how you feed that information back into the design flow."
Assuming that lithography will continue to be one of the main limiting factors in ramping a fab, the trend toward more simulation will continue, Charrier said. "You need some mechanism that the designers and the manufacturing people can talk to each other. And it turns out that lithography simulation is the way that you can do that."
Thomas Blaesi, vice president of marketing and business development at Sigma-C (Santa Clara, Calif.), agreed, noting that lithography simulation has changed from being simply for litho engineers to use for optimization to being a bridge between the process and the design. As illustrated in Figure 1, there was typically a wall between cell/chip development and process development. But lithography simulation is becoming more and more necessary to bridge the gap between the pattern on a mask and the desired outcome on a wafer. As shown in the top of Figure 1 , designers can design a chip or cell, then apply optical proximity correction (OPC) to it. In so doing, they can use the same simulation library into which process engineers are feeding information about calibrated resist models, or dose and focus variations, or various types of lenses, or any number of other possible process parameters.
 |
| 1. Lithography simulation is becoming more necessary to bridge the gap between cell/chip development and process development. (Source: Sigma-C) |
Process development
But before DFM (design for manufacturing) was the current buzz word, lithography engineers were using simulation software to do process development tasks, Charrier said. "When they were going from 0.35 µm to 0.25 µm, well, the lithography process engineers at our customers had to decide — okay, are we going to move to deep UV scanners, 248 scanners? Or can we stay with the i-line 365 scanners? And how robust will our process be if we stay with the i-line?"
Lithography simulation continues to be a good way to make decisions about all kinds of trade-offs: quadrupole illumination vs. annular, what type of resist to use, etc. Lithography engineers can answer these questions before they even get the tools in the fab, Charrier said, and they can also answer questions about existing tools. "You have a question you need to answer about a process you already have. Well, you have a choice. You can either run 30 wafers through your fab and take your very expensive scanner down for a few hours, or you can run simulation for a couple hours, and basically you do virtual wafers using the simulation, get your answer close, and then you go off and run a few wafers — but not the 30 that you otherwise would've needed."
In addition to entering into the design space, litho simulation has also become more prevalent in the fab, according to Blaesi. Besides the process developers, fab engineers have also begun to use the software to optimize processes. One example Blaesi gave was when a fab receives a mask, and the mask is slightly out of specification. By simulating the parameters of the mask and the various tools in the fab, an engineer can figure out which tool would produce the best yield for that mask. This is one way to do tool selection. "There are many more examples where you could use litho simulation to debug a process," Blaesi said. "If you have a sudden yield loss, you can debug your process or fab line by using litho simulation."
Full-chip simulation
Although lithography simulation has been a part of the product development cycle for some 15-20 years, full-chip simulation has been used for just about four years to do model-based OPC, according to John Sturtevant, RET technical support manager of the Design to Silicon Division at Mentor Graphics Corp. (Wilsonville, Ore.). In that time, full-chip simulation has become a critical part of the litho process. "If there's any fab running today at 130 or below, you can be absolutely sure that they're using full-chip simulation," he said.
Full-chip simulation is a complementary activity to the traditional desktop litho simulation tools, mostly relegated to production rather than process development. Full-chip simulations use massive computing resources to achieve higher speeds, but there is a trade-off between speed and accuracy. Also, unlike desktop simulators, full-chip simulation relies on a calibrated model, noted Sigma-C's Blaesi. "You run certain test structures through the fab, extract the data, and basically fit the model. And it's only valid for one process point," he said. But what is becoming increasingly common is for lithographers to keep tweaking the process even after it's in the fab, in an ongoing effort to optimize the process for yield. So a full-chip simulator might identify hot spots or weak spots in a design, and then customers could use Sigma-C's Solid+, for example, to analyze the weak spots and drill down further.
"Anything that's semi-empirical, you've got to calibrate," Sturtevant agreed. "It used to be that you could get the accuracy that you needed with relatively few distinct measurements on a wafer. But the number of measurements that's required has just exploded. It's approaching 10,000 or more that need to be fed in." Figure 2 shows the number of CD measurements needed in relation to the process node — growing from only ~20 measurements needed at the 180 nm node.
 |
| 2. Moving from the 180 to 45 nm node, there has been an exponential increase in the number of CD measurements required to calibrate and OPC model. At almost 10,000 measurements for the 45 nm node, this number is estimated to reach almost 100,000 by the 22 nm half-pitch. (Source: Mentor Graphics) |
Because of this, Mentor has a newer approach to calibration based on CD-SEM images. Essentially, it takes a picture of a structure that may, for example, have 50 or 100 gates inside the field of view. It feeds that image into the system and relates it to GDS information. "Now instead of taking 15 hours to get 10,000 discrete measurements, you can get it in 15 seconds," Sturtevant said.
Last year, Mentor introduced OPC Verify, which does full-chip simulation on the design after OPC treatment. OPC Verify uses a type of simulation that has not been typically used in full-chip software — grid-based simulation rather than sparse or polygon-based simulation, Sturtevant explained. TCAD tools for process development engineers have always been based on the idea of overlaying a two-dimensional grid over the design, with simulations done all along the grids. But because of the need for speed, full-chip programs a more sparse approach.
In the earlier days of lithography, this made sense because, looking at any given poly edge, there might only be a couple of nearest neighbors that would have any influence on the design, Sturtevant explained. But that situation is changing as lithography pushes to lower and lower k1 . "What we found is that, as you go closer to 65 and into 45 and down into 32, of course geometrically the spaces are getting smaller and smaller and smaller, so you're packing in more and more features, yet we're still using 193 nm light, and we're incrementally raising the NA," Sturtevant said. "But the effective k1 is such that, now, if I go look at the edge of that gate of interest, now instead of only a couple nearby patterns having an influence, now it's dozens of nearby patterns that are having an influence. And now, when you think about overlaying that mesh grid over an entire design vs. where the simulation points would've been if you just placed them along the fragments of the edge, there's a crossover in efficiency where it starts to make sense to do so-called grid-based simulation."
Speed vs. accuracy
In the full-chip arena, simulation tool providers are always balancing accuracy with runtime. Part of the reason full-chip simulation systems are able to run as fast as they can is because of distributed processing on multiple CPUs, routinely using 50 or 100 CPUs on a 65 nm design to get the turnaround time that they need. Still, full-chip simulation takes a hit on accuracy in order to provide more speed, so any changes geared toward improving accuracy generally come with a speed penalty.
But while speed has become of the essence in semiconductor manufacturing, so to has the demand for accuracy increased. Critical features at the 90 nm node, for example, may need something along the lines of 5 nm CD control, Blaesi noted. "At 65 nm, the range goes to 3 nm. At 45 nm, it's a range of 1 nm CD control," he said. "You have to be more and more accurate to understand what happens to your process."
Brion's Wiley agrees. "Many of our customers have told us, if you think about the whole litho process, the accuracy of the model and the accuracy of the OPC itself is now the dominant error factor in the entire litho process," he said. "It's not how good is the stepper, it's not how good is the resist — it's how good is the simulation and the control of the placement of the features."
The Holy Grail of litho simulation is to take any given pattern with a known film stack, a known resist behavior, etc., and model the full chip concurrently with the OPC, noted Wolf Staud, product manager of RET solutions, DFM, at Cadence. "There is no server in the world that could ever handle that thing. If you link up all the CPUs that we have available worldwide, you probably would never finish that job," he said. "So people still need to make abstractions. They need to lump parameters together."
 |
| 3. This simulation example from the Virtuoso RET suite demonstrates the concept of lithography-aware design, which allows viewing of lithography capabilities for different RET approaches in the layout environment. (Source: Cadence) |
"Really, the accuracy doesn't suffer from full chip. Things can be as accurate as you want them to be," Synopsys's Weed said. "There's just a constant trade-off in terms of how much do you simulate and the accuracy that you get for what you're simulating and the time it takes to do that."
The continuing theme, Sturtevant noted, is how to incrementally add treatment for optical phenomena that represent a larger part of the budget as feature sizes shrink. "Our philosophy is usually to make sure we've got the most robust modeling capabilities out there," he said. "So we give those knobs to the user, and it's really up to them to determine what trade-offs are they willing to make in terms of runtime."
For full production tapeouts for foundries and IDMs, it's all about turnaround time and time to market, so speed is the key. So that's where the full-chip simulation typically comes in. On the flip side, the desktop simulators do not trade off accuracy, Blaesi said. "We are very accurate and we have certain limitations: runtime and area," he said. But even the traditional litho simulation tools are now able to do multiprocessing, thereby improving area and speed while keeping accuracy on a high level, Blaesi added. "Today we can do 20 µm × 20 µm, but with parallel processing we can go up to 100 µm × 100 µm." For the future, there will continue to be a big effort to increase area without giving up accuracy, he said.
"Given that accuracy cannot be compromised while doing process development for the advanced technology nodes of today and tomorrow, we need to come up with innovative methods of improving speed such that it is less of a trade-off between speed and accuracy," Bettadapur agreed.
With the desktop systems getting faster, the lines between the traditional and full-chip simulation tools are beginning to blur. Likewise, the full-chip systems are finding new ways to gain accuracy without sacrificing speed. According to Wiley, Brion broke away from the traditional speed vs. accuracy trade-off by putting its simulation into FPGA-accelerated dedicated computing boards, bringing the accuracy closer to a desktop system at a rate faster than traditional full-chip simulators.
Sturtevant noted that Mentor's software is starting to break away from its traditional role in simulation for full-chip correction of designs. "Increasingly, we're seeing that customers are using Calibre more for that litho process development mode — both for making predictions in sensitivity analysis, and also for process optimization. Things like, what is the right numerical aperture to use for this process? What's the right illumination settings — quadrupole or annular or whatever? And that's I think a tribute to the accuracy of the tool, even though it's designed to be very high-speed for full-chip use."
Some ideas for the future
In their pursuit of faster speeds and higher accuracy, simulation tool providers are capitalizing on their own strengths to develop new ideas to fulfill future simulation requirements. MaskTools and Cadence, for example, are leveraging their three-way relationship with leading exposure tool supplier ASML to provide a higher level of optimization through proprietary knowledge of the exposure tool.
 |
| 4. Done in LithoCruiser, these simulations show a 2-D cross-section of how a resist would perform at best focus and out of focus. (Source: ASML MaskTools) |
 |
| 5. Multi-algorithm 3-D EMF tools such as KLA-Tencor’s Prolith, which uses both Rigorous Coupled Wave Analysis (RCWA) and Finite Difference Time Domain (FDTD) algorithms, offers fast and accurate insights into new mask technologies and mask manufacturing artifacts on the final printed image. (Source: KLA-Tencor) |
Full-chip simulators are increasingly, especially at 45 nm, required to account for variability, Sturtevant said. The models must be able to account for process drift, with accuracy through the process window rather than just the best conditions. This will require calibrating the model at multiple parameters. In some regards, lithography simulation is becoming so accurate that it exceeds the metrology tools' ability to measure it against the actual fab processes. "The metrology tools themselves have error in them, as much as we don't like to talk about it, but they do," Charrier said. "So you can measure the exact same line two times, and you might get a 1 nm difference from the number that you get out of the tool. And of course, if you do the simulation twice, you get exactly the same answer — there's no random error there." The idea that KLA-Tencor has started working on is to take its knowledge of how metrology tools work and put that into the lithography simulation software to better match what the tools say the numbers are coming off the wafers.
| References |
|
|
