Sony Demonstrates Feasibility of Copper/ULK (2.0) Interconnects

In the past several years, Japanese firms have been at the forefront of low-k dielectric scaling. At the recent International Interconnect Technology Conference (IITC), Shinichi Arakawa and colleagues at Sony Corp. (Kanagawa, Japan) demonstrated copper interconnect structures with a hybrid polyarylene (PAr)/SiOC structure for the 32 nm node. The process is characterized by a low-k hard mask (k=2.65) and a new pore-sealing process that uses an organic gas plasma treatment (OPT). The approach yielded an 11% reduction in capacitance without degradation of time-dependent dielectric breakdown (TDDB) or electrical properties. The OPT significantly improved stress migration (SM) and electromigration (EM) performance.

The Sony team used a newly developed protection hard mask process that replaced a conventional triple hard mask process (TEOS/SiN/low-k) to better control the dual-damascene profile. In the conventional process, low selective etching of SiN hard mask to low-k hard mask led to poor profile control. The protection hard mask/low-k hard mask scheme allowed higher selectivity and better profile control while avoiding ashing.

Introduction of a low-k hard mask (k=2.65) resulted in an 11% reduction in interline capacitance relative to a conventional hard mask. The engineers compared the electrical properties of 75 nm vias (300k) and 36 m metal lines of 75 nm width and found no difference in resistance distribution between the different hard mask materials. The 75 nm space TDDB reliability results showed that the lifetime of the low-k hard mask (2.65) structure is almost the same as that of the conventional and low-k (2.9) hard mask structures, indicating that the lower-k material was successfully integrated.

For comparison purposes, the Sony team fabricated the 2.65/PAr/ultralow-k (ULK) stack (Figure ), as well as a 2.65/PAr/dense SiOC (2.65) stack. Via resistance results of the dense SiOC vs. the ULK for 75 nm vias and 3M chains were comparable, with good via chain yields and resistance distributions. However, the via resistance in the ULK was slightly higher because of a smaller via size. With the ULK, interlevel capacitance was reduced by 18%.

Ultralow-k (2.0) is used at the via level, while polyarylene (k=2.3) is integrated at the line level with low-k (2.65) hard mask.

Reliability studies showed that a pore-sealing process was needed for ULK. Two processes were investigated using a spacer on the via sidewall or plasma treatment with an inert or organic gas (Table ). In the spacer process, a selective etch to the SiOC ULK is performed after the conventional PECVD SiO₂ or CH_x polymer deposition. However, this process may be complicated to apply to 32 nm interconnects because of difficulty of conformal film deposition, etch controllability and trench-bottom sealing. The plasma treatment enables isotropic sealing, so it should be more compatible at 32 nm. SM results on via chains with 3 µm wide metal lines and 75 nm vias under thermal stress (400 hr, 225°C) looked for a 10% resistance change. It was confirmed that the OPT using organosilane was most effective against SM degradation.

EM testing at 325°C and 1 MA/cm² in 26 via chain structures showed a 3× longer mean time to failure with OPT vs. without pore sealing. To investigate the mechanism of reliability improvement, thermal desorption spectroscopy, as well as contact-angle measurements, was performed on ULK blanket wafers that were prepared with reactive ion etch and wet processes, assuming a dual-damascene process. OPT led to the recovery of the contact level to the bulk ULK value, indicating the damaged surface layer of the ULK was restored by the OPT. Measurement of the amount of oxygen in the barrier metal with and without pore sealing (after 400°C anneal) led to a decrease of oxygen content of 67% with pore sealing. OPT suppresses moisture uptake, preventing barrier metal oxidation.

The Sony team concluded that low-k hard mask and pore-sealing technologies are breakthrough integration schemes for reliable 32 nm node interconnect fabrication. An OPT serves to improve SM and EM reliability by suppressing moisture uptake in ULK films and barrier metal oxidation. A hybrid PAr/SiOC structure is successfully fabricated with a low-k (k=2.65) hard mask, achieving significant reductions in interlevel capacitance.