TI Announces 45 nm Process

Texas Instruments released the details of its 45 nm manufacturing process last month, including a variety of improvements to processes and materials. The end result was a projected 30% increase in performance, a 40% reduction in power consumption and, through the use of immersion lithography, the ability to double the number of chips produced on each wafer.

Although the company won't have 45 nm in production for some time and still has some process issues to resolve, the announcement is a signal that TI is confident enough of future capability to release the new specs to designers so they can start incorporating them into new projects. TI's 45 nm process will be manufactured on 300 mm wafers in the DMOS6 facility in Dallas. The low-power ASIC design library will be available by the end of this year, with samples of the first system-on-a-chip (SoC) product delivered in 2007 and initial production in mid-2008.

Improved performance and power consumption are more critical than ever as consumers demand the ability, for example, to run more simultaneous applications such as a game with 3-D graphics in parallel to a video conference between the players, with e-mail synchronizing in the background. Reducing power by 40% will allow longer video playback time and up to 30% longer cell phone standby time.

In many ways, the 45 nm technology is more evolutionary than revolutionary, still relying on planar transistors and bulk silicon (as opposed to multigate transistors and silicon on insulator [SOI]). Although many see more advanced (and more complicated) transistor structures, such as the finFET, as inevitable, there are manufacturing challenges that have yet to be resolved. "A whole lot of collateral changes are needed to get to that kind of device, not the least of which is that you have induced step height at key lithography levels that we traditionally work very hard to eliminate," said Ben McKee, vice president of silicon technology development for 45 nm at TI. "As long as we can increment material and move forward with the same kind of a structure, that's how we will most quickly put cost-effective technology into production."

Multiple TI 45 nm transistors showing contacts and transistors (top), and a complete transistor for TI’s 45 nm low-power process (bottom).

Evolutionary tendency aside, TI has made some notable advancements with 45 nm. For the first time, the company will implement the use of 193 nm immersion lithography, which has enabled researchers to develop what they believe to be the smallest 45 nm SRAM memory cells, occupying only 0.24 µm² — up to 30% smaller than other 45 nm memory cells announced to date. Memory cells are often the first development vehicle for new manufacturing technologies, and they provide valuable data about transistor densities that will be achieved on complete SoCs.

For the first time, TI is also using millisecond anneals for junction formation and moving to a more high-aspect-ratio isolation approach with conformal fill. A collection of strain techniques will enhance transistor performance and minimize leakage for all three versions of the process, including TI's first use of silicon germanium in its strain application. "We started using strained silicon at 90 nm, and of course we tune and optimize as much as we need to get to the right level of performance," McKee said. "The higher-performance ones will have silicon germanium as well as the stress memorization and dual stress liners."

45 nm will employ TI's third-generation process technology to use low-k dielectrics for reducing capacitance and propagation delays within a device's interconnect layers. "We're moving from the 2.9 class down to 2.5," McKee said. That equates to a little more than 15% total reduction in pure film, and a little bit more than 10% reduction in effective k (k_eff). "We lose some with the barrier dielectrics, but not all."

Finally, TI is considering techniques to cost-effectively enhance performance through the use of a dual work function metal gate at some point in its 45 nm technology roadmap. Options include the use of full silicidation of polysilicon (FUSI) or a combination of metal plus a silicide. Currently being explored for the highest-performance process, TI believes leveraging a metal gate with continued use of proven silicon nitrided dielectrics delivers the necessary power consumption control without having to simultaneously move to new, more complex high-k materials. "FUSI is a less invasive move to metal, but we're also working on a deposited refractory metal approach because it's a step toward high-k," McKee said. High-k materials are seen as a necessary replacement for today's very thin gate dielectrics, typically silicon dioxide or a silicon oxynitride. "We've still got a few quarters worth of work left looking at the opportunity from a FUSI or deposited metal for that choice."

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