Optimizing the Interface Between Design and Manufacturing

The resolution enhancement technique (RET) design flow has become a conglomeration of various point tools and methodologies. Deep subwavelength design for manufacturing (DFM) requirements have forced the design and manufacturing communities into very tight collaboration. The EDA industry is also driven to provide an infrastructure to facilitate communication for these communities. Having this infrastructure in place has a direct impact on productivity and quality.

A key part of this infrastructure for communication is a modeling file called the Process Model File (PMF) — a way to consolidate the information used in simulations where each tool in a flow can access what it needs. Process and design details can be passed between lithography, integration, design, layout, verification and tapeout groups. This creates a portable modeling kit that unifies the entire RET design flow. Therefore, tool setup and simulation results are consistent throughout the flow.

Without the sharing of this information, there is a breakdown in design quality as the industry moves down technology nodes. Design rule check (DRC) clean layout is hardly a qualifier for lithography yield anymore. The big push at tapeout time is still an enormous effort when little or no care is given for RET requirements during the lengthy design phase. Consider the entire investment of time for a product design, which can take several months to complete. Meanwhile, the tapeout schedule is still constrained to a few days or less. The entire development paradigm from design to production must fundamentally change.

The benefits of using an infrastructure where process information can be shared are extremely valuable. However, the information must also be protected. Sensitive parameters and routines can be optionally masked while still made available for simulation or execution.

This system has great value for small to large organizations that may be of the foundry, IDM or fabless type. The cost benefits can be realized by generating an "RET-friendly" layout, eliminating design respins, having clean RET verification, and meeting tapeout schedules.

The RET challenge

With the help of new EDA tools and flows, designers are starting to embed design information in manufacturing data, permitting downstream tools to optimize analysis on structures that are critical to the design. However, new design tools are emerging that allow designers to apply more proactive methods to ensure compliance with downstream lithographic requirements. Sophisticated design rule sets that encode lithographic constraints are allowing these tools to identify and correct problematic structures well before tapeout, creating a new methodology called "lithography-aware design."

Consider the various flows and methodologies that exist for lithography-aware design. All are based on the assumption that a predictive or calibrated lithography model is accurate enough to cover all the design variations. Months are sometimes required to perform fine-tuning and validation of that one model. In many cases, the calibrated model is only accurate enough for one layer and focus condition. Today, the industry is seeing the exploration of through-process window models that allow a more robust "hot spot" detection method. There are also various ways to score a layout and find marginal areas of printability.

1. Lithography-aware design solutions re-quire that manufactur-ing capabilities be seamlessly communi-cated to the design community, which passes design intent to manufacturing.

The end effect is that all design data must eventually pass through some sort of RET treatment and lithography simulation using one or more models. Doing so during the lengthy design cycle also helps uncover critical flaws in the process early on when changes have the least economical penalty. Similar to DRC, a designer is eager to validate the layout before proceeding with more exhaustive electrical verification and simulations. Any layout change forces them to go back and recheck everything. Things like signal integrity, electromigration, CMP effects, parasitics and so forth are simulated and tested only after the layout if in a fixed condition. Lithography simulations can also be very time-consuming and compute-intensive, but there is no free lunch. Whatever shortcuts or tricks are used will always trade off between performance and accuracy.

Hot spot example

Let's examine the possible sources of a hot spot error, the various groups involved and why a portable PMF plays an important role:

Group 1: The lithography process and model calibration — The limitation of what can be printed is a function of not just the scanner wavelength, but also many physical effects that come into play at the subresolution nodes.

With advanced simulation tools, a scanner and resist process can be optimized. Furthermore, these unique characteristics can be captured and used within the PMF. For example, a variety of measured illuminator profiles can be added to the PMF, in addition to one or more calibrated models, and used in a variety of simulation tools downstream (Fig. 2 ). This gives other engineers in the design chain the opportunity to test other conditions that may fall outside the space of the calibrated models provided.

2. Scanner and reticle performance optimized and exported for lithography-aware design via secure Process Model File (PMF).

Once a model is calibrated (Fig. 3 ) and appears in the form of Hopkins kernels, then this information is otherwise lost. The PMF also enables better closed-loop feedback for lithography engineers who pass their current process snapshot to designers and allow them to exercise various test patterns or layout for printability. It is important to realize that the amount of layout engineers that exist in an organization almost always outnumber the amount of lithography or integration engineers. Therefore, having the ability to do quick iterations among a broad community of intended recipients of your final lithography recipe adds immense value to the whole process and shortens the cycle by which an optimal process condition is converged upon.

3. Model calibration is critical for accurate OPC. Actual resist SEM image shows precise agreement with modeled image.

Group 2: Design rules — In the early stages of design rule creation, there is a need to have quick iterations of process changes and layout feasibility studies. Once the lithography process has been relatively fixed, the next phase is to formulate the design rules by which layout designers will hopefully abide. The assumption is that an exhaustive analysis of various layout scenarios has been done, and these design rules will give the proper budget needed by the RET treatment process to converge properly. This may mean that enough space is given to add the correct amount of edge biasing or subresolution assist features. Some double-exposure technologies might even have other additional rules for polygon placement. In order to give designers some flexibility on certain rule restrictions, a secondary set of DFM recommended rules is often issued. This lets the designer choose his or her own fate. In some cases, the layout cannot be sacrificed in order to implement the recommended rules (Fig. 4 ).

4. Post-tapeout layout may not allow an OPC insertion that meets design rule requirements.

Group 3: Retargeting rules and model OPC recipe — The RET treatment process is a highly complex process of transforming layout data into mask data, which can be reproduced with enough fidelity so that all the process variations of the mask house and foundry are accounted for in the final wafer results. The first assumption here is that the manufacturing process variability can be modeled accurately and used in a treatment engine to add just the right amount of compensation in the mask data. The second assumption is that the design rules have given a sufficient budget in the layout to add all the rule/model-based corrections needed. To give a boost to the model-based treatment, there is often a rule-based implementation that happens first. It may involve retargeting rules where certain edge configurations are biased. Perhaps some hammerheads and scatterbars are also applied. This alleviates the load on the model optical proximity correction (OPC) engine and aids faster convergence. The OPC recipe itself is a complex script where a geometry engine can break up the target edges into smaller pieces for iterative movement/evaluation cycles. This works in combination with a simulation engine that uses the lithography model to find the optimal placement of all the moving edges. Performance is improved when edges are broken up into fewer segments; however, the accuracy and finer compensation is sacrificed. When more segments are generated, the runtimes and file sizes go up (Fig. 5 ).

5. RET treatment is a highly complex process of transforming layout data into mask data, which can be reproduced with enough fidelity so that all the process variations of the mask house and foundry are accounted for in the final wafer results. PMF simplifies the recipe storage in this process.

Group 4: Post-RET verification setup — The verification of post-RET data is extremely compute-intensive. It is now standard practice to apply massive computing resources to perform the complex task of simulating the mask data and detecting hot spots. With multiple process window conditions, this amounts to guardbanding a contour output from the model(s) and then comparing against the target layer(s). The users are then faced with the challenge of what to do when they find trouble areas. The assumptions here are that the model is trusted, the DRCs are clean, and the OPC recipe has done its job. Now a hot spot is found and the question arises as to what the root cause is. Often times, a sanity check is needed with a SEM image at the same location as a hot spot to determine if the prediction was accurate. The last possibility is that the setup of the RET verification tool was somehow not done properly and is now giving false or over/under-pessimistic reports.

What to do about any given area of concern is still a major challenge for all EDA suppliers. Each design flow can be dramatically different and likewise have different requirements. Redirecting the hot spot to the appropriate point in the flow for corrective action is what makes having the PMF so valuable. The offending piece of data can then be analyzed by the various groups 1-4 using the PMF contents.

Integrated approach

The lithography-aware design methodology is an integrated approach of having lithography simulation capability during the early design stages. The ability to check a layout with confidence requires the four groups previously discussed to each contribute and build a PMF whereby the post-RET verification can be done seamlessly (Fig. 6 ). The result of verification is only as good as the treatment, which is considered within the boundary of the design rules. Finally, the design rules are within the boundary of the lithography process to which a model has been calibrated.

6. The lithography-aware design methodology is an integrated approach of having lithography simulation capability during the early design stages. The ability to check a layout with confidence requires the four groups pictures to each contribute and build a PMF, whereby post-RET verification can be done seamlessly to prevent hot spots at the design source.

Integration of the PMF into the pre-tapeout stage — or design environment — is what makes it so valuable (Fig. 7 ). The integrated approach for lithography-aware design is especially valuable because of the ever-increasing cost of design respins. Getting it right the first time is what's on every designer's mind. The ability to fix hot spots in the post-tapeout stage is fine unless you hit a point where the actual layout, design rules, or lithography process has been found to need correction.

7. PMF integration to the design environment allows lithography expertise to be encapsulated and transported to the background of the design environment, eliminating the need for designers to become lithography experts.

Conclusion

No one denies that the design and manufacturing communities must communicate more effectively. In fact, as we approach more advanced process nodes, this communication is a downright necessity. An infrastructure to enable this close communication, and at the same time optimize the interface between design and manufacturing, has been described in this article.

The PMF should be regarded as an enabling technology. It is an infrastructure by which critical modeling and recipe information can be passed both upstream and downstream. This channel of communication will allow faster ramp of new technology nodes, as well as doing designs right the first time. The PMF itself can be secured to not reveal its contents, while at the same time allows a designer to execute and see results as dictated by the security switch settings. This can be delivered to a designer in the form of a kit with a similar look and feel to DRC. It is also extendable to support other types of processes, including CMP, etch and particle analysis models (Fig. 8 ).

8. Various tools that use a PMF show the power, continuity of providing lithography capability to the design, post-treatment verification, maskmaking, and wafer-manufacturing environments.