Yield: Part of Bigger Productivity Picture

Cost of ownership and the bottom line drive manufacturing decisions now more than ever. This is ever-apparent in the critical area of yield management, where capital spent to improve yield must also be justified. But it is not like the old days prior to advanced process control and equipment control. Today, yield management is part of a larger productivity picture in the fab that can and is being looked at from the enterprise level. All the pieces of yield are being brought together. Yield management encompasses defect detection and characterization, wafer environment contamination control and monitoring, yield learning, yield modeling, ramping, management, and continuous improvement. It includes wafer yield, probe yield, parametric yield, packaged device yield, and analysis of failed product.

The greatest challenges for the industry? Not unlike in other areas, it means achieving higher yields faster with fewer false starts (capture of nuisance defects), better feedback loops, and capturing all the relevant yield hits for new materials in front-end-of-line (FEOL) and back-end-of-line (BEOL) processes during a fast ramp up.

Interestingly, in its quest for wafer-level control (WLC) of variation, the industry has not found integrated metrology (IM) to be a suitable drop-in replacement for standalone metrology that it once might have appeared to be. This was examined in detail in our cover story in June by Advanced Micro Devices (AMD).¹ Instead, AMD is finding that processes rarely exhibit within-lot instability, and most of the wafer-level variation is actually a combination of systematic contributions from upstream equipment. Key drivers in determining what control strategy should be adopted include factory efficiency, yield enhancement and cost effectiveness. IM complements standalone metrology as process and factory needs change, and it helps with pattern-limited yield. With the combination of standalone metrology and dynamic sampling, the company was able to produce WLC that approaches the performance of wafer-to-wafer feed-forward control with IM.¹ In the 2005 International Technology Roadmap for Semiconductors (ITRS), the Yield Enhancement working group identified four key topical areas: yield modeling and defect budget, defect detection and characterization, yield learning, and wafer environment(s) contamination control. In Semiconductor International's recent technology webcast series, the Electronics Manufacturing Summit (www.emsummit.com), technology working group chair Lothar Pfitzner summarized the overall chapter, while co-chair Kevin Pate of Intel elaborated on the wafer environment contamination control section.

As features scale, one of the greatest challenges is increasing inspection sensitivity and reducing the amount of background noise detected in the process. Because systematic defects typically dominate sub-130 nm processes, systematic yield loss mechanisms must be identified and eradicated through logic diagnostic capability, which, again, must be high in throughput. Greater sensitivity and throughput are needed for defect detection, review and classification routines. The latest version of the ITRS summarizes the needs for rapid yield learning well: "Automated, intelligent analysis and reduction algorithms, which correlate facility, design, process, test and work-in-progress (WIP) data, will have to be developed to enable rapid yield learning."

We summarized the most important near-term (M32 nm) difficult challenges in yield enhancement in our January issue.² Because the detection of particles at the critical size may not exist, fabs may have to settle for detection of defects on or about the size of the critical dimension (depending on the process step). One of the growing needs is to measure line-edge roughness and be able to correlate such features to device leakage and performance. High-aspect-ratio feature inspection has been an ongoing concern, especially for memory manufacturers, but also in logic with the vast populations of contacts and vias. E-beam inspection does not meet the throughput requirements for this application.

Looking at the long-term difficult challenges, of course, nothing gets easier with respect to yield enhancement. Today, there is little correlation between type of contaminant and yield. For instance, some organic materials may have a greater impact on device yield than other organic contaminants. Wafer bevel and edge regions must be better controlled. Parametric-sensitive yield models are needed.

The defect budget target calculations for the 2005, 2003 and 2001 ITRS were all based on results of three studies of particle per wafer pass (PWP) levels at Sematech member companies (2000, 1999 and 1997). These targets were extrapolated from median PWP value per generic process tool type, and then scaled to microprocessor- and DRAM-generic process flows. A negative binomial model is used, where overall die yield is the product of systematic and random defect-limited yield. Table 1 shows the yield and product maturity assumptions used to calculate electrical fault density values and PWP defect budget targets for MPUs and DRAMs. Table 2 is an excerpt of the random PWP defect budget targets necessary to meet the stated assumptions for a cost-performance MPU with primarily logic transistor functionality and a small cache.