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Nanotech Offers Continuance of Moore's Law

Alexander E. Braun, Senior Editor -- Semiconductor International, 6/15/2006

Sidebars:
Nanotechnology Executive Viewpoints

Since practically its beginning, Moore's Law has been semiconductor technology's prime mover, with silicon as the vehicle of implementation. As feature sizes continue to shrink and new materials have to be introduced, characterized and domesticated, the industry is looking toward nanotechnology as the means to continue this unparalled technical advancement.

Nanotech's potential is dizzying. Fueled by its unique capability to combine multiple fields ranging from chemistry and biology to quantum mechanics and materials at molecular and atomic levels, it should be able to put to rest for a very long time any concerns about staying abreast of Moore's Law. Of course, first we will have to solve assembly and manufacturing hurdles, and the R&D effort and expenditures this will require promise to be far from minor.

There is a silver lining to these concerns, not the least of which being that, in terms of feature size, the semiconductor industry has been involved with nanotech for well over three decades. For example, e-beam lithography was used in the 1970s to create 60 nm features. What makes it different now is that, although it appears more than likely that silicon will still be with us 20 years from now — possibly up to 20 nm and perhaps beyond — the problems that we will face at the end of that period are beginning to become visible.

But don't sell CMOS short. Much of what we hear about nanotech, as it applies to the semiconductor industry, is the blue-sky stuff that conference papers are made of. When microprocessors and various forms of computers are designed for specific purposes, plain old CMOS (with little change in technology) is used. There is still considerable room for improvement in CMOS technology when it comes to making certain tasks more computationally intensive.

From today's perspective, this is a more technological and cost-effective way of tackling these problems. As Steve Simon, director of theoretical physics research at Bell Labs, puts it, "If you want a single, very fast transistor, some of the III-V technologies are already better. Alternative technologies being considered originate from different platforms, different structures, and different starting points. Even if they were as good as CMOS (none of them are), you're still short a trillion dollars in investments in getting to CMOS's level. There are changes — not necessarily fundamental — to CMOS, which could have substantial effects upon what can be done at a larger scale. Things like optical interconnects on CMOS chips — there's still a lot of blood left in the CMOS stone."

Alhough most everyone looks to carbon nanotubes as the answer to the question of what comes after silicon's demise, there are still too many questions and uncertainties to be conquered and dispelled, not the least of which is how to place them, how to ensure that they grow into the desired structures, and finally whether they will be capable of matching silicon's reliability. It took many generations of engineers and uncountable millions to turn silicon into the familiar workhorse it is now; it is very likely that a similar kind of effort will be necessary with nanotubes.

Broadly speaking, there are presently two approaches to creating nano devices. Rapidly shrinking toward nanoscale is the top-down approach, in which a silicon wafer is etched and various films deposited. The second is the bottom-up approach, the kind most think about when "nanotech" is mentioned. Here, molecules and nanotubes are built to construct devices. Currently, it appears we will have to do both.

According to the International Technology Roadmap for Semiconductors (ITRS), we will use the top-down approach for the next decade. Beyond then, technology leaders like Intel expect to be using silicon nanowires and possibly carbon nanotubes. At that time, we should have a clearer idea of what building blocks will provide the most robust and commercializable technology.

TechXPOT: Emerging Technologies

Tuesday, July 11: Nano Materials & Manufacturing Technologies
2:40-3 p.m.Intel, Mike Garner
3-3:20 p.m.TIS Winner: Cambrios Technologies, Hash Pakbaz
3:20-3:40 p.m.TIS Winner: Pixelligent Technologies, Kenneth Rygler
3:40-4 p.m.TIS Winner: NanoDynamics, Karen Buechler
4-4:20 p.m.Surfx, Robert Hicks
4:20-4:40 p.m.Nano Green, Suraj Puri
Thursday, July 13: Nano Metrology
2:20-2:40 p.m.TIS Winner: ALIS Corp., John Notte
2:40-3 p.m.TIS Winner: Metryx, Liam Cunnane
3-3:20 p.m.TIS Winner: Ascend Instruments, Joseph Robinson

 

Nanotechnology Executive Viewpoints

Ilesanmi Adesida, Prof. of Engineering & Dean of the College of Engineering, University of Illinois at Urbana-Champaign, Bell Labs

I expect that conventional silicon nanotechnology will continue to be developed to its full potential, albeit in an accelerated manner, over the next many years as projected by the ITRS. A critical survival element at the device level is high-k dielectric; SiO2 is already only three or four atomic layers in demonstrated devices, and new dielectrics will allow a degree of latitude in device fabrication. When one considers the truly new elements for nanoscale devices involving nanotubes, various nanowires, and quantum dots, there are still many showstoppers that must be contended with in order to see one's way forward. Although carbon nanotubes have excellent electronic properties, a severe problem is the lack of control on the placement of individual elements, and for other types of nanowires, surface depletion effects must be solved. Molecular electronics need materials with predictable properties. A bridge to these new types of devices may be a revival of III-V semiconductor devices at nanoscale. InGaAs-, InSb-, and InAsSb-based heterostructure field-effect transistors are being developed. Being able to grow these materials on silicon will be a breakthrough. This cannot be discounted since GaN materials are now grown on silicon with excellent device performance; therefore, applying similar growth techniques may open an avenue for III-V devices for ultrahigh integration.

Ahmed Busnaina, Director, NSF

If we consider new developments along the scaling down of traditional semiconductor nano manufacturing techniques, a few of these may be along the nanolithography front. We may start seeing production EUV lithography tools exhibited in the next year or two.

Also, with the new announcement that immersion lithography has been shown to work down to 31 nm, we could expect immersion lithography to challenge EUV for the 32 nm node. On another front, in a couple of years or so, we may start seeing tools for new dry cleaning technologies that are still under development. These could include laser shock cleaning, supercritical, and many other techniques under developments.

On the non-semiconductor side, new techniques for building devices of nanotubes or nanowires will likely begin seeing the light in a few years. This is especially true for those technologies that are compatible and integrable with CMOS. We are already seeing the use of single-wall nanotubes (SWNTs) for devices as mechanical switches, which will replace transistors. Some electronics manufacturers are working on using SWNTs or semiconducting nanowires as transistors. Many of these techniques apply existing semiconductor manufacturing techniques, making them CMOS-compatible. As for directed-assembly techniques (for nanotubes, nanowires, etc.), they are still a few years (5-10) ahead before we see a manufacturing tool that could be employed on a large scale and high throughput with nano-scale features.

D.M. Tennant, Technical Manager, Advanced Lithography Group, Nanofabrication Research Dept., Lucent Technologies, Bell Labs

Nanotech is a subject that encompasses such a broad array of applications and technologies that its trend and impact cannot be singularly assessed. One of the areas of interest to Bell Labs involves integrating MEMS with ICs to create new applications.

A few years ago, most MEMS structures were much larger than features on ICs, and it was difficult to label the work as nanotechnology. Today, the requirements for the MEMS layer are rapidly approaching — and in some cases exceeding — IC dimensions and alignment tolerances. Higher levels of integration for SoC applications that combine actuators or sensors with ICs in advanced packages appear to be a strong trend. We have already seen how large-scale arrays of binary mirrors have impacted the HDTV industry. In the future, even higher-density and more massive arrays of multi-position mirrors may replace the photomask in lithography systems.

Whether the product is a mirror array or a chemical or bio sensor, the tool set traditionally used for IC manufacture is, with only modest changes, also used to fabricate the functional layers. Much of this work, therefore, leverages the huge prior investment made for ICs.

The interesting question is whether there is a driver for companies to make an IC size investment in "system fab" facilities to make the full design space available for integrating actuators, sensors and other high-function structures with state-of-the-art circuits. Without such investment, yield limitations and process compatibility will relegate these sectors to either hybrid assembly methods, such as flip-chip and multi-chip modules, or to very simple mechanical layers known to be compatible with IC thermal budgets and reliability. Ushering in the next generation of MEMS/IC technology will rely on such an investment by companies looking ahead to tomorrow's markets and industries.

Find more information on nanotechnology.
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