Interconnect Issues Going Into 45 nm

Several trends are making interconnect processing more challenging as the industry moves to more advanced technology nodes. One is the issue of resistance variability, which is a function of things such as across-wafer variability of CMP, etch and other processes, making process control paramount. Parametric variation is an overall challenge below 100 nm, not just for interconnects.

Another issue is the size effect — the increased resistivity of copper as linewidths shrink below around 100 nm and approach the mean free path of electrons in copper (39 nm). The resistivity increase is caused by electron scattering at the surface of the line and at grain boundaries. Fortunately, the estimations of the magnitude of the effect the size effect has on interconnect delay has been overestimated. For at least the next few device generations, the size effect can be effectively managed through interconnect design, including keeping local interconnects short. In addition, a change of barrier material would have little effect on the intrinsic surface scattering of copper (Figure ).¹

Finally, current density is increasing because the size of the lines is shrinking, yet the current flowing through the copper is the same. The thinner lines must be better protected from electromigration. Cobalt capping layers would help in this regard, but there are other levels of redundancy that chipmakers are employing.

A thin-film scattering of large grain copper for a variety of barrier films. Resistivity vs. thickness is consistent with 100% diffuse scattering in all cases. (Source: Novellus)

In advanced logic devices, where most companies have successfully made the transition to copper interconnects and the first generation of low-k dielectrics (k~2.9), the resources are now being invested in second-generation low-k (~2.5) for the 45 nm node. Beyond curing, other film treatments are being developed to give films the necessary electrical properties without having to occupy the same footprint. For second-generation low-k, the challenge largely lies in developing damage- and moisture-resistant films that can undergo dual-damascene processing and packaging via flip-chip and wire bonding.²

Reliability in copper interconnects is tied to the weakest interfaces, inducing stress migration and electromigration phenomena. The other major mode of electrical failure is time-dependent dielectric breakdown associated with weaker dielectrics. Therefore, building reliable interconnects comes down to engineering interfaces and managing stresses in the on-chip stack, as well as stresses through the off-chip assembly and packaging process.

Memory manufacturers are expected to start adopting copper next year. Unlike the logic manufacturers, some memory makers adopted some form of low-k dielectric prior to making a metallization change from aluminum to copper. Aluminum metallization processes have been extended many ways, including with advanced CVD processes.

From a unit process standpoint, the greatest need seems to be for an ALD barrier solution that would allow more drastic scaling of the barrier, which leads to an equivalent lower k_eff without changing the dielectric. But the magical Ta/TaN PVD barrier will continue to be extended for now. Likewise, while CoWP capping processes are being made more manufacturable, better dielectric caps will continue to be developed. It is unclear whether CoWP capping layers will ever be implemented in manufacturing or if an alternative copper metallization scheme will come along.