Front-End Advances Strengthen Performance
Peter Singer, Editor-in-Chief -- Semiconductor International, 6/15/2006
The semiconductor industry has continued its push to
ever-smaller dimensions, moving to a new technology generation every two to
three years. Leading-edge volume production is now moving from 90 to 65 nm, and
R&D work is focused on next-generation 45 and 32 nm. The International
Technology Roadmap for Semiconductors (ITRS) has these generations slated to
move into production in 2009 and 2011, respectively, although Intel has already
demonstrated working 45 nm chips earlier this year, with a stated production
goal of 2007 on 300 mm wafers (Fig. 1 ).
Semiconductor processing is often separated into "front end" and "back end" steps, with front end referring to the fabrication of the transistors, and back end referring to the on-chip "wiring" or interconnects. For the 45 and 32 nm generations, much of the industry's focus will be on the front end, since that is where the biggest gains in performance are expected. The two biggest goals are to reduce leakage current and increase speed. Leakage current is particularly important for low-power chips used in mobile applications, since excessive leakage current both consumes power and increases heat.
There has been great interest in three-dimensional transistor structures, most notably the finFET. The advantage of this type of a device is that the gate of the transistor is wrapped around the channel region, enabling more effective control of drive and leakage current (i.e., the current when the device is on and off). Although there has been significant progress in understanding the many manufacturing challenges associated with putting such devices in production (mostly lithography and cleaning challenges), it does not look like 3-D structures will come into play for the 45 nm generation. Instead, the focus will be on strained silicon, which can boost overall chip speed by a whopping 40% compared with non-stressed devices.
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| 1. Intel plans to start fabricating devices with 45 nm technology on 300 mm wafers starting in 2007. A wafer with SRAM test chips is shown. (Source: Intel) |
As shown in Figure
2 , strain engineering involves straining of the silicon crystal to increase the mobility of charge carriers in the channel (electrons in NMOSFETs and holes in PMOSFETs). An added benefit is that it reduces the source/drain series resistance. Compressive strain is induced in PMOS transistors, typically using epitaxially grown SiGe source/drain and/or a compressively strained nitride layer over the gate. The greatest emphasis is given to the PMOSFET, since hole mobility is typically three orders of magnitude less than electron mobility. In NMOS transistors, a tensile-strained nitride layer is used. These processes induce approaches that have proven to be the most manufacturable and cost-effective, and were first implemented in manufacturing at the 90 nm node. Another method that can be used is biaxial strain or global strain, where the entire wafer is strained by various methods. This approach is not likely to enter manufacturing until the 32 nm node or later because of defectivity and integration issues. However, it is expected to complement process-induced (primarily uniaxial) approaches at some point.1
Beyond the use of strain, there is a focus on new materials for the gate stack. Traditionally, the gate is made up of a heavily doped polysilicon electrode, separated from the channel region by a very thin dielectric, typically SiO2
or more recently, SiON. The thinness of this dielectric is important in that a thinner dielectric allows for more coupling of the charge from the gate into the channel, which increases drive current and switching speed. If it is too thin, however, excessively high leakage current can result to the point where the off current is almost as high as the on current. A possible solution lies in higher-k dielectrics, most notably hafnium-based silicates. The higher k value enables more charge to be coupled through a thicker material. The problem is one of integration: Higher-k materials have shown to have adhesion problems and also some potential electrical problems related to Fermi pinning, which can cause a shift in threshold voltage (which determines when a transistor turns on and off).
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2. Four stress techniques — dual stress liners, stress memorization (SM) and an embedded SiGe source/drain — were fully integrated on a partially depleted SOI substrate. (Source: IBM and AMD)
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Initially, it was thought that the push to high-k dielectrics would bring with it a requirement for a move from polysilicon to metal gates. But now metal gates have emerged as a major performance-enhancer, even without high-k. Full silicidation of polysilicon gates (FUSI), particularly using nickel, has become an attractive approach to integrating metallic gates into CMOS devices for low-power applications. Advantages include the compatibility with mainstream polysilicon front-end processing, nickel silicide's mid-gap work function, and the possibility of work function tuning by ion implantation. In addition, since the silicidation takes place at a relatively low temperature, it can be performed after junction activation. However, some of the challenges with FUSI processing include gaining full silicidation on all features and integrating FUSI with minimal impact to the CMOS process. But perhaps the greatest concern is scalability. If companies are going to make a high-k/metal gate change in manufacturing, perhaps a single change to high-k and dual-function metal gates is preferable to an intermediate change to oxynitride/FUSI (a single-generation solution) or high-k/FUSI, only to eventually change to high-k/metal gates.1
TechXPOT: Challenges in Device Scaling
Tuesday, July 11: Engineered Substrates |
| New developments in engineered substrates appear every week in the literature. SOI, silicon on glass, DBS, and layer transfer technology to give localized orientation, SiGe or III-V layers. Why are they needed? Which of the new substrates will be implemented when? |
| Session Chair: Mayank Bulsara, Altas Technologies |
| 2:30-2:35 p.m. | Atlas Technologies, Mayank Bulsara —Introduction |
| 2:35-3 p.m. | Chipworks, Dick James — Status of Engineered Substrates |
| 3-3:20 p.m. | Freescale Semiconductor, Ted White —The Need for Engineered Substrates |
| 3:20-3:40 p.m. | MEMC, Bruce Kellerman — Wafer Manufacturer Perspective |
| 3:40-4 p.m. | SiGen, Francois Henley — SiGen Approach |
| 4-4:20 p.m. | Soitec, Bruno Ghyselen — Soitec Approach |
| 4:20-4:30 p.m. | Atlas Technologies, Mayank Bulsara —Wrapup |
| Wednesday, July 12: Advanced Processes for Advanced Devices |
| Conventional CMOS is nearing its scaling limits. Device makers are going to high-k dielectrics, process-induced strain, and non-conventional device structures to keep performance in line with Moore's Law. What are the scaling limits for CMOS? What performance advantages do the new devices bring? How will they be integrated into production? |
| Session Chair: Ken Monnig |
| 2-2:20 p.m. | IMEC, Serge Biesemans — New Materials and Architecture |
| 2:20-2:40 p.m. | Amberwave Systems Corp., Tony Lochtefeld |
| 2:40-3 p.m. | Praxair Electronics, David Thompson |
| 3-3:20 p.m. | TBA, Equipment Supplier — ALD, epi, CVD for strain engineering |
| 3:20-3:40 p.m. | TBA — Surface Preparation |
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