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DFM Becomes More Than Hype

Laura Peters, Senior Editor -- Semiconductor International, 6/15/2006

Sidebars:
DFM Executive Viewpoint

The flurry of startup activity in the design for manufacturing (DFM) space has led some people to joke that the acronym really stands for "design for merger," because some companies structure themselves as good targets for eventual acquisition. But really, DFM has become a legitimate sector of the industry, now that real tools are helping real companies prevent zero functional yield at first silicon — the event that began the DFM craze not too many years ago.

DFM came about because of the mismatch between the precisely constructed and followed design rules and layouts and the chip yield on printed silicon. Subwavelength lithography has largely been the cause of this mismatch, but not the sole contributor. Process variability, smaller process windows, power integrity issues, and changing defect mechanisms also play a role in driving a need for a better relationship between IC design and manufacturing. When process nominal yields from test chips do not match actual yields, designers suddenly needed to concern themselves with more than power and timing issues, and branch into areas involving leakage currents, electromigration and modeling at lower supply voltages. From the manufacturing side, systematic mechanism-limited yield loss, which has become the biggest source of yield loss in advanced chips, is tied to the design. DFM is needed to address the biggest source of yield loss.

Most of the early DFM products targeted optical proximity correction (OPC) — first rule-based, then model-based corrections that accommodate the complexity of the design. Tools have been developed to start with the best focus and exposure conditions, but to then test the output throughout the process window to see if the design will print correctly. Now, the methodologies and tools are branching into new areas — no longer just concerned with such first steps as adding redundant vias, checking process windows, and performing verification on verification.

Because the industry is only now beginning to realize the effects of process and yield variation, it is also only beginning to understand the role that DFM will play in the overall yield and productivity picture. Certainly, this is a new area of expertise for which engineers with talent on both sides of the aisle are sorely needed, and will be much appreciated in the years to come.

TechXPOT: Manufacturing Productivity & Effectiveness

Tuesday, July 11: Design for Manufacturing
The theme of this session is on the broad area of design for manufacturability (DFM), with talks that focus specifically on DFM incentives and solutions to the issues generally accepted in the IC industry.
Agenda:
11-11:20 a.m.Rsoft Design Group, Brent Whitlock — Photonic Design Automation (PDA) Software for Lithography and Optical Metrology
11:20-11:40 a.m.Stratosphere Solutions, Jim Bordelon — Sub-100nm Parametric Variability
11:40 a.m.-12 p.m.Mentor Graphics, Joe Sawicki — Process Variability and its Impact on the Layout
12-12:20 p.m.Ponte Solutions, Ara Markosian — Yield Management Platform for Designers
12:20-12:40 p.m.Pyxis Technology, Naeem Zafar — DFM: Necessitating Revolution Throughout the Flow
Wednesday, July 12: Growing Smaller Together: Collaboration Below 90 nm
This session will look at the issues being exacerbated by the advances of the industry into ever-finer feature sizes. These issues of increasing statistical variations, the need for much more accurate power and noise modeling, and the requirement for all of the design elements to be handled in a unified way throughout the design and manufacturing process need immediate attention to prepare for the move into 65 nm processes and beyond.
Agenda:
11-11:30 a.m.Si2, Sumit DasGupta
11:30 a.m.-12 p.m.Si2, Nick English
12-12:20 p.m.TIS Winner: Straatum, Marcus Carbery — Imprint MX3, Multi-Sensor FDC
12:20-12:40 p.m.TIS Winner: Seaware Technologies, Scott Hepworth — Semiconductor Process Performance Validation

 

DFM Executive Viewpoint

Richard Brashears, Corporate Vice President, Cadence Design Systems

Moving to advanced manufacturing technologies, semiconductor companies are finding that modifying physical design data to improve yield can actually impact IC performance and functionality. Designers are now focusing on manufacturing effects at the earliest possible stages of design, and looking to accurately predict on-chip performance variation caused by downstream CMP and lithography steps. Conventional DFM approaches rely only on rough estimates of downstream effects and have not been able to provide the accurate data necessary for reliable prediction. Practical use of "manufacturing-aware" design flows, though, has been difficult because of the challenge in balancing yield-enhancing manufacturing requirements with performance-optimizing design requirements.

Traditionally, fabs have communicated data about manufacturing effects to designers through design rules for a particular process and fab. By following these rules, companies could anticipate nominal yield levels. Today, advanced process technologies have altered the complexity and nature of design rules to the point where "required" rules are augmented with "optional" but recommended rules that can be used to achieve higher potential from a new process technology. Unfortunately, the increasing interaction between physical layout and subwavelength lithography and chip planarization effects significantly impacts yield ramp and maximum yield. In this environment, successful IC development depends on the ability to accurately predict the impact of these manufacturing effects.

At this year's SEMICON West, we'll see emerging methodologies that draw on model-based approaches to provide the data needed to optimize both performance and yield. These approaches comprehend manufacturing constraints and allow designers to position shapes and optimize interconnect topologies in the precise configurations and locations necessary to satisfy manufacturing and yield objectives, while anticipating downstream electrical effects. This flexible modeling approach serves as a key enabler for manufacturing-aware IC design methodologies and development flows.

Find more information on DFM.
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