Critical Tailoring of Clean Processing

The most prevalent and most critical of all semiconductor manufacturing process steps is wafer cleaning. Over the years, it has evolved to a point where not only must most cleans be specifically tailored to the preceding or subsequent fabrication step (i.e., pre- or post-cleans), but to a level of sophistication that is better labeled as surface preparation or surface engineering. Not only must contamination be removed, but also the clean processing must be damage-free, corrosion-free and highly selective with minimal material loss. Add to that the influx of a vast array of new materials — many in production with many more in research — as well as the trend to smaller, more complex features and you have the makings of one of the most dynamic technologies in the industry.

Perhaps surprisingly, though, a technology developed in the '60s — a two-step wet clean best known as the RCA clean — has proved amazingly resilient and it, or at least a modified version of it, is still in wide use today. Wet cleaning/surface preparation has in general proved to be the technique of choice. Concerns that it would be difficult to impossible for any water/chemicals to get in and out of increasingly narrow features with higher aspect ratios have, at least so far, proved to be groundless. A vast amount of research has been done to develop alternatives, including concepts that include dry cleaning in a high-vacuum environment, supercritical cleans (which require a fairly high pressure), laser shock cleaning and cryogenic aerosol jet cleaning. Despite some dramatic successes, however, the industry still remains largely married to wet cleaning. In part, this is because wet cleaning has continued to mature and evolve with the introduction of new technologies, such as the use of dilute chemistries, ozonation, megasonics and single-wafer cleaning. As noted in the latest International Technology Roadmap for Semiconductors (ITRS), "Wet chemical critical cleaning is still favored because many inherent properties of liquid solutions facilitate the removal of metals (high solubility in liquid chemistries) and particles (zeta-potential control, shear stress and efficient energy transfer by megasonics). The need for other techniques will arise, however, to provide interfacial control for advanced gates as well as non-etching, damage-free particle removal."¹ Continued success will depend on how well existing technologies meet the needs of new materials, such as high- and low-k dielectrics, metal gates, epitaxial SiGe, etc., and increasingly small and fragile structures like that found in the finFET.

New cleaning techniques, such as water aerosol and cryogenic aerosol, have been implemented in manufacturing as single-wafer systems. Other techniques for cleaning, such as laser and supercritical CO₂ (SCCO₂) processes, are experiencing a high level of R&D and, if implemented, most likely will be on a single-wafer system. However, the barriers for acceptance of these techniques are high, because solutions for cleaning already exist. Chemistries used for cleaning will continue to evolve. Dilute chemistries, especially RCA cleans, have shown feasibility and are used in production. Because they can lead to less attack of the oxide and silicon surfaces, dilute chemistries have gained greater acceptance in most advanced fabs. Ozonated water processes are being implemented as replacements for some sulfuric acid-based resist strips and post-cleans. The use of ozonated water does reduce the use of chemicals and water; however, the implementation is not widespread because of the slow processing times and potential for corrosion. In addition, new resist formulations for 193 nm lithography may pose challenges for ozonated water resist stripping, as well as for sulfuric acid-based resist stripping.

Potential solutions are only indicated for the near-term years (through 2009), as it is unclear what challenges will exist for surface preparation at the 22 nm technology generation. As in the past, it is expected that current and future surface preparation processes will be the subject of continuous improvement efforts.¹ The utilization of SCCO₂-based technology in wafer cleaning presents a number of advantages, including excellent mass-transfer phenomena (lack of surface tension) and enhanced ultralow-k compatibilities. Organic solvents or proprietary chemical blends are frequently used as modifiers to improve cleaning performance.

Successful back-end-of-line supercritical cleans of 90 and 65 nm wafers using both bench-top and 300 mm tools have already been conducted. Although the implementation of this new technology is expected to be further delayed, its unique properties and capabilities continue to draw interest for cleaning applications in future technology nodes.²